AD9778_15 Datasheet, PDF (44/56 Pages) Analog Devices – Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters

AD9776/AD9778/AD9779
Using Data Delay to Meet Timing Requirements
To meet strict timing requirements at input data rates of up to
250 MSPS, the AD977x has a fine timing feature. Fine timing
adjustments are made by programming values into the data
clock delay register (Register 0x04, Bits<7:4>). This register can
be used to add delay between the REFCLK in and the
DATACLK out. Figure 97 shows the default delay present when
DATACLK delay is disabled. The disable function bit is found
in Register 0x02, Bit 4. Figure 98 shows the delay present when
DATACLK delay is enabled and set to 0000. Figure 99 indicates
the delay when DATACLK delay is enabled and set to 1111.
Note that the setup and hold times specified for data to
DATACLK are defined for DATACLK delay disabled.
TEK RUN: 5.00GS/s SAMPLE
Δ: 4.48nS
@: 40.28nS
2
1
CH1 1.00VΩ CH2 500mVΩ M2.00ns
CH1 420mV
Figure 97. Delay from REFCLK to DATACLK with DATACLK Delay Disabled
TEK RUN: 5.00GS/s SAMPLE
Δ: 4.76nS
@: 35.52nS
2
1
CH1 1.00VΩ CH2 500mVΩ M2.00ns
CH1 420mV
Figure 98. Delay from REFCLK to DATACLK Out with DATACLK Delay = 0000
TEK RUN: 5.00GS/s SAMPLE
2
Δ: 7.84nS
@: 32.44nS
1
CH1 1.00VΩ CH2 500mVΩ M2.00ns
CH1 420mV
Figure 99. Delay from REFCLK to DATACLK Out with DATACLK Delay = 1111
The difference between the minimum delay shown in Figure 98
and the maximum delay shown in Figure 99 is the range
programmable using the DATACLK delay register. The delay
(in absolute time) when programming DATACLK delay
between 0000 and 1111 is a linear extrapolation between these
two figures. The typical delays per increment over temperature
are shown in Table 20.
Table 20. Data Delay Line Typical Delays Over Temperature
Delays
−40°C +25°C +85°C Unit
Delay Between Disabled and 370 416 432 ps
Enabled
Average Delay per Increment 171 183 197 ps
The frequency of DATACLK out depends on several program-
mable settings: interpolation, zero stuffing, and interleaved/
dual port mode, all of which have an effect on the REFCLK
frequency. The divisor function between REFCLK and
DATACLK is equal to the values shown in Table 21.
Table 21. REFCLK to DATACLK Divisor Ratio
Interpolation Zero Stuffing Input Mode
1
Disabled
Dual port
2
Disabled
Dual port
4
Disabled
Dual port
8
Disabled
Dual port
1
Disabled
Interleaved
2
Disabled
Interleaved
4
Disabled
Interleaved
8
Disabled
Interleaved
1
Enabled
Dual port
2
Enabled
Dual port
4
Enabled
Dual port
8
Enabled
Dual port
1
Enabled
Interleaved
2
Enabled
Interleaved
4
Enabled
Interleaved
8
Enabled
Interleaved
Divisor
1
2
4
8
Invalid
1
2
4
2
4
8
16
1
2
4
8
Rev. A | Page 44 of 56