ADSP-BF531SBB400 Datasheet, PDF (43/64 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test and Emulation Port Timing
Table 36. JTAG Port Timing
Parameter
V_DDEXT = 1.8 V
Min
Max
V_DDEXT = 2.5 V/3.3 V
Min
Max
Unit
Timing Requirements
t_TCK TCK Period
t_STAP TDI, TMS Setup Before TCK High
t_HTAP TDI, TMS Hold After TCK High
t_SSYS System Inputs Setup Before TCK High¹
t_HSYS System Inputs Hold After TCK High¹
t_TRSTW TRST Pulse Width² (Measured in TCK Cycles)
Switching Characteristics
20
20
ns
4
4
ns
4
4
ns
4
4
ns
5
5
ns
4
4
TCK
t_DTDO TDO Delay from TCK Low
t_DSYS System Outputs Delay After TCK Low³
10
10
ns
0
12
0
12
ns
1 _{System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,}
RESET, NMI, BMODE1–0, BR, PPI3–0.
2 _{50 MHz maximum}
3 _{System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,}
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t_TCK
t_STAP
t_DTDO
t_DSYS
t_SSYS
t_HTAP
t_HSYS
Figure 31. JTAG Port Timing
Rev. H | Page 43 of 64 | January 2011