ADAU1702_15 Datasheet, PDF (41/52 Pages) Analog Devices – SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs

ADAU1702
ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER
Table 48. Serial Input Control Register Bit Map
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
0
0
ILP
IBP
M2
M1
M0
0x00
Table 49. Serial Input Control Register Bit Descriptions
Bit Name
Description
ILP
INPUT_LRCLK polarity. When this bit is set to 0, the left channel data on the SDATA_INx pins is clocked when
INPUT_LRCLK is low and the right channel data is clocked when INPUT_LRCLK is high. When this bit is set to 1,
the clocking of these channels is reversed. In TDM mode, when this bit is set to 0, data is clocked in starting with
the next appropriate BCLK edge (set in Bit 3 of this register) after a falling edge on the INPUT_LRCLK pin. When
this bit is set to 1 and the device is running in TDM mode, the input data is valid on the BCLK edge after a rising
edge on the word clock (INPUT_LRCLK). INPUT_LRCLK can also operate with a pulse input, rather than a clock;
in this case, the first edge of the pulse is used by the ADAU1702 to start the data frame. When this polarity bit is
set to 0, use a low pulse; when the bit it set to 1, use a high pulse.
IBP
INPUT_BCLK polarity. This bit controls on which edge of the bit clock the input data changes and on which
edge it is clocked. Data changes on the falling edge of INPUT_BCLK when this bit is set to 0 and on the rising edge
when this bit is set at 1.
M[2:0]
Serial input mode. These two bits control the data format that the input port expects to receive. Bit 3 and Bit 4
of this control register override the settings of Bits[2:0]; therefore, all four bits must be changed together for
proper operation in some modes. The clock diagrams for these modes are shown in Figure 32, Figure 33, and
Figure 34. Note that for left-justified and right-justified modes, the LRCLK polarity is high and then low, which is
the opposite of the default setting for ILP.
When these bits are set to accept a TDM input, the ADAU1702 data starts after the edge defined by ILP. Input
the ADAU1702 TDM data stream on Pin SDATA_IN0. Figure 35 shows a TDM stream with a high-to-low triggered
LRCLK and data changing on the falling edge of the BCLK. The ADAU1702 expects the MSB of each data slot to
be delayed by one BCLK from the beginning of the slot, as it would in stereo I²S format. In TDM mode, Channel 0
to Channel 3 are in the first half of the frame, and Channel 4 to Channel 7 are in the second half. Figure 36 shows
an example of a TDM stream running with a pulse word clock, which is used to interface to ADI codecs in auxiliary
mode. To work in this mode with either the input or output serial ports, set the ADAU1702 to begin the frame
on the rising edge of LRCLK, to change data on the falling edge of BCLK, and to delay the MSB position from the
start of the word clock by one BCLK.
Setting
Function
000
I²S
001
Left justified
010
TDM
011
Right justified, 24 bits
100
Right justified, 20 bits
101
Right justified, 18 bits
110
Right justified, 16 bits
111
Reserved
Rev. C | Page 41 of 52