ADAU1401_15 Datasheet, PDF (41/52 Pages) Analog Devices – SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs

Data Sheet
ADAU1401
2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
Table 48. Serial Output Control Register Bit Map
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
0
0
OLRP OBP M/S OBF1 OBF0 OLF1 OLF0 FST
D5 D4 D3 D2 D1 D0 Default
TDM MSB2 MSB1 MSB0 OWL1 OWL0 0x0000
Table 49.
Bit Name
OLRP
OBP
M/S
OBF[1:0]
OLF[1:0]
FST
TDM
MSB[2:0]
OWL[1:0]
Description
OUTPUT_LRCLK Polarity. When this bit is set to 0, the left-channel data is clocked when OUTPUT_LRCLK is
low and the right-channel data is clocked when OUTPUT_LRCLK is high. When this bit is set to 1, the right-
channel data is clocked when OUTPUT_LRCLK is low and the left-channel data is clocked when
OUTPUT_LRCLK is high.
OUTPUT_BCLK Polarity. This bit controls on which edge of the bit clock the output data is clocked. Data
changes on the falling edge of OUTPUT_BCLK when this bit is set to 0 and on the rising edge when this bit is
set to 1.
Master/Slave. This bit sets whether the output port is a clock master or slave. The default setting is slave; on
power-up, the OUTPUT_BCLK and OUTPUT_LRCLK pins are set as inputs until this bit is set to 1, at which time
they become clock outputs.
OUTPUT_BCLK Frequency (Master Mode Only). When the output port is being used as a clock master, these
bits set the frequency of the output bit clock, which is divided down from an internal 1024 × fS clock (49.152
MHz for a fS of 48 kHz).
OBF[1:0]
Setting
00
Internal clock/16
01
Internal clock/8
10
Internal clock/4
11
Internal clock/2
OUTPUT_LRCLK Frequency (Master Mode Only). When the output port is used as a clock master, these bits set
the frequency of the output word clock on the OUTPUT_LRCLK pins, which is divided down from an internal
1024 × fS clock (49.152 MHz for a fS of 48 kHz).
OLF[1:0]
Setting
00
Internal clock/1024
01
Internal clock/512
10
Internal clock/256
11
Reserved
Frame Sync Type. This bit sets the type of signal on the OUTPUT_LRCLK pins. When this bit is set to 0, the
signal is a word clock with a 50% duty cycle; when this bit is set to 1, the signal is a pulse with a duration of
one bit clock at the beginning of the data frame.
TDM Enable. Setting this bit to 1 changes the output port from four serial stereo outputs to a single 8-
channel TDM output stream on the SDATA_OUT0 pin (MP6).
MSB Position. These three bits set the position of the MSB of data with respect to the LRCLK edge. The data
output of the ADAU1401 is always MSB first.
MSB[2:0]
Setting
000
Delay by 1
001
Delay by 0
010
Delay by 8
011
Delay by 12
100
Delay by 16
101
Reserved
111
Reserved
Output Word Length. These bits set the word length of the output data-word. All bits following the LSB are
set to 0.
OWL[1:0]
Setting
00
24 bits
01
20 bits
10
16 bits
11
Reserved
Rev. C | Page 41 of 52