ADV7172 Datasheet, PDF (40/59 Pages) Analog Devices – Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management

ADV7172/ADV7173
BRIGHTNESS CONTROL REGISTERS (SCR)
(Address (SR5–SR0) = 21H)
The brightness control register is an 8-bit-wide register which
allows brightness control. Figure 66 shows the operation under
control of this register.
SCR BIT DESCRIPTION
Reserved (SCR7–SCR5)
A Logic “0” must be written to these bits.
Brightness Control Value (SCR4–SCR0)
These five bits represent the value required to vary the “brightness
level” or pedestal added to the luma data. The available range is
from 0 IRE to 7.5 IRE in 18 steps. A value of 18 (10010) corre-
sponds to 7.5 IRE setup level added onto the pixel data. This
brightness control is possible in both PAL and NTSC.
SHARPNESS RESPONSE REGISTER (PR)
(Address (SR5-SR0) = 22H)
The sharpness response register is an 8-bit-wide register. The
four MSBs are set to “0.” The four LSBs are written to in order
to select a desired filter response. Figure 67 shows the operation
under control of this register.
PR BIT DESCRIPTION
Reserved (PR7–PR4)
A Logic “0” must be written to these bits.
Sharpness Response Select Value (PR3–PR0)
These four bits are used to select the desired luma filter re-
sponse. The option of twelve responses is given supporting a
gain boost/attenuation in the range –4 dB to +4 dB. The value
12 (1100) written to these four bits corresponds to a boost of
+4 dB while the value 0 (0000) corresponds to –4 dB. For nor-
mal operation these four bits are set to 6 (0110).
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SCR7–SCR5
ZERO SHOULD
BE WRITTEN
TO THESE BITS
SCR4–SCR0
BRIGHTNESS VALUE
Figure 66. Brightness Control Register
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
PR7–PR4
ZERO SHOULD
BE WRITTEN
TO THESE BITS
PR3–PR0
SHARPNESS RESPONSE
SELECT
Figure 67. Sharpness Response Register
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REV. A