AD9887A_15 Datasheet, PDF (40/52 Pages) Analog Devices – Dual Interface for Flat Panel Display

AD9887A
SYNC Detection/Active Interface Control
0x11 7 Analog Interface HSYNC Detect
This bit is used to indicate when activity is detected on
the HSYNC input pin (Pin 82). If HSYNC is held high or
low, activity is not detected.
Table 30. Analog Interface HSYNC Detection Results
Detect
Function
0
No activity detected
1
Activity detected
Figure 43 shows where this function is implemented.
0x11 6 Analog Interface Sync-on-Green Detect
This bit is used to indicate when sync activity is detected
on the sync-on-green input pin (Pin 108).
Table 31. Analog Interface Sync-on-Green Detection Results
Detect
Function
0
No activity detected
1
Activity detected
Figure 43 shows where this function is implemented.
Warning: Even if no sync is present on the green video
input, normal video might trigger activity.
0x11 5 Analog Interface VSYNC Detect
This bit indicates when activity is detected on the
VSYNC input pin (Pin 81). If VSYNC is held high or
low, activity is not detected.
Table 32. Analog Interface VSYNC Detection Results
Detect
Function
0
No activity detected
1
Activity detected
Figure 43 shows where this function is implemented.
0x11 4 Digital Interface Clock Detect
This indicates when activity is detected on the digital
interface clock input. Because this register is unreliable
in certain applications, an external DVI clock detect
shown in Figure 28 is recommended.
Table 33. Digital Interface Clock Detection Results
Detect
Function
0
No activity detected
1
Activity detected
Figure 43 shows where this function is implemented.
0x11 3 Active Interface (AI)
This bit indicates which interface should be active,
analog or digital. It checks for activity on the analog and
digital interfaces, then determines which should be
active according to the conditions outlined in Table 34.
Specifically, analog interface detection is determined by
OR’ing Bit 7, Bit 6, and Bit 5 from this register.
Digital interface detection is determined by Bit 4 in this
register. If both interfaces are detected, the user can deter-
mine which has priority via Bit 6 in Register 0x12. The
user can override this function via Bit 7 in Register 0x12.
If the override bit is set to Logic 1, this bit is forced to the
set state of Bit 6 in Register 0x12.
Table 34. Active Interface Results
Bits 7, 6, or 5 Bit 4
(Analog
(Digital
Detection) Detection) Override¹
0
0
0
0
1
0
1
0
0
1
1
0
X
X
1
AI^{2, 3}
Soft power-down
(seek mode)
1
0
Bit 6 in Register 0x12
Bit 6 in Register 0x12
1 _{The override bit is Bit 7 in Register 0x12.}
2 _{AI = 0 means analog interface.}
3 _{AI = 1 means digital interface.}
0x11 2 Active Hsync (AHS)
This bit determines which Hsync to use for the analog
interface, the HSYNC input or the sync-on-green. It uses
Bit 7 and Bit 6 in this register for inputs when determining
which should be active. Similar to the previous bit, if both
Hsync and sync-on-green are detected, the user can deter-
mine which has priority via Bit 4 in Register 0x12. The
user can override this function via Bit 5 in Register 0x12.
If the override bit is set to Logic 1, this bit is forced to the
set state of Bit 4 in Register 0x12.
Table 35. Active Hsync Results
Bit 7
Bit 6
(HSYNC Detect) (SOG Detect)
0
0
0
1
1
0
1
1
X
X
1 _{The override bit is Bit 5 in Register 0x12.}
2 _{AHS = 0 means HSYNC input.}
3 _{AHS = 1 means SOG input.}
Override¹
0
0
0
0
1
AHS^{2, 3}
Bit 4 in
Register 0x12
1
0
Bit 4 in
Register 0x12
Bit 4 in
Register 0x12
Rev. B | Page 40 of 52