UG-487 Datasheet, PDF (4/8 Pages) Analog Devices – iCoupler EVAL-ADuM5010EBZ, 150 mW isoPower Evaluation Board

UG-487
EMI MITIGATION
The PCB implements EMI mitigation techniques discussed
in the AN-0971 Application Note to demonstrate the
recommended board layout options for this device. These
techniques include stitching capacitance and edge guarding.
Stitching Capacitance
The capacitance between the primary and secondary power
and ground planes is the most effective way to reduce high
frequency emissions from an isoPower device. Figure 2
shows how the inner layers of a PCB can create this stitching
capacitance by overlapping inner layer metal to create an
extremely low inductance capacitance. The green area shows
the active coupling area.
Edge Guarding
Providing guard rings laced together with vias on each layer
of the primary side reduces edge emissions from the PCB
LAYER 2 GROUND
Evaluation Board User Guide
stack-up. This addresses emissions due to large high frequency
vertical current flow through vias and traces near the edges.
Figure 4 shows the top layer guard ring and the bottom layer
ground fill as well as the regularly spaced vias in the guard ring
that creates a cage type structure to reflect inter-plane emissions
back into the PCB. Figure 5 shows the top layer power fill along
with its vias to the Layer 3 power plane. This top layer power
fill adds distributed capacitance as well as shielding for the
layer below.
HIGH VOLTAGE CAPABILITY
This PCB is designed in line with 2500 V basic insulation
practices. High voltage testing beyond 2500 V is not recom-
mended. Appropriate care must be taken when using this
evaluation board at high voltages, and it should not be relied
on for safety functions since it has not been hi-pot tested or
certified for safety.
LAYER 3 POWER
OVERLAP
CREATING CAPACITANCE
Figure 2. Ground and Power Planes Creating Stitching Capacitance
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