SHA1144 Datasheet, PDF (4/6 Pages) Analog Devices – HIGH RESOLUTION 14 BIT SAMPLE AND HOLD AMPLIFIER

OPERATION WITH AN A/D CONVERTER
Figure 6 below shows the appropriate connections between
the SHA1144 and a successiveapproximation A/D converrer
in block diagram form.
OPERATIONWITH AN A/D AND MULTIPLEXER
The subsystemof Figure9 may alsobe connectedto a multi-
plexerlike the HarrisHI508A asshownbelow.
sHAl144
INPUT OUTPUT
'l
CHANNEL 1 INPUT
o,o,,o.
OUTPUT
MODE
CONTROL
-J
CHANNEL 6
CONVERT
COMMAND
Figure6. SHAI144 andA/D Connections
The resultingtiming sequenceat the start of conversionis illus-
tratedin Figure7.
CONVEFT
INPUT
Figure 9. A/D, SHA,and MPX Connections
sHA1144
INPUT
OUTPUT
SIGNALS
sHAl 144MOOE
'I
CONVERT
CoMMAND
o
STFTUSOUTPUT/ 1
MOOECONTROL _n
INPUT
SWITCHINGTRANSIENT
SETTLING - lai
The leading edge of the convert command pulse sets the
STATUS output to Logic ^"0" thereby switching the SHAl144
to ^"hold"; the correspondingchangeto Logic ^"1" of the
STATUS output increments the binary counter and changes
the multiplexer address.Since the SHA1144's aperture time is
small with respect to the multiplexer switching time, it will
have switched to the hold mode before the multiplexer actu-
ally changeschannels. The multiplexer switching transients
will settle out long before the SHA returns to ^"sample" at the
end of conversion. The timing sequencedescribed above is
illustrated in Figure 10.
Figure 7. A/D and SHA Timing at Start of Conversion
Note that the leading edgeof the convert command pulse causes
the converter'sSTATUS output to go to Logic ^"0" which in
turn switchesthe SHAl144 from sampleto hold. As discussed
previously,the typical SHA1144 actually changesmodes 50
to 50.5nsafter the ^"1." to ^"O" transition of the mode control
input. This mode switching causesa transient on the output
terminal which decays to within 0.0037o of the final value in
approximately ltrts.Once the transient has settled, the convert
command input is returned to Logic ^"0" and the conversion
proceeds. As shown in Figure 8, the STATUS signal returns
to Logic ^"l" and the SHAl144 returns to the samplemode
at the end of conversion. Within 6gs, it will have acquired the
input signalto O.0O37oaccuracy and a new conversioncycle
may be started.
33ill'^lt
ffiooJ,'#I1".u,
r,YlJlll,:*"
+10v
MULTIPLEXER
OUTPUT/
SHA INPUT
OV
_ 10 _v
S H 4 1 1 4 4M O D E
+10v
SHAOUTPUT/
ilD TNPUT
MNEL
-l 0v
gEtTG
sHAl 144
INPUT/
OUTPUT
SIGNALS
SHA114M/t ODE
SfFfu-S ourPUT/ _l
M O D EC O N T R O L
INPUT
U
Figure 8. A/D and SHA Timing at End of Conversion
Figure 10. A/D, SHA, and MPX Timing
This method of sequencing the multiplexer may be altered to
permit random addressingor addressingin a preset pattern.
The timing of the multiplexer addresschangesmay also be
altered but corisideration should be given to the effects of
feedthrough in the SHA1144. Feedthrough is the coupling of
analog input signalsto the output terminal while the SHA is
in ^"hold". Large multiplexer switching transients occuring
during A/D conversion may introduce an error.
-L-