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OP297_06 Datasheet, PDF (4/16 Pages) Analog Devices – Dual Low Bias Current Precision Operational Amplifier
OP297
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
Input Voltage1
Differential Input Voltage1
±20 V
±20 V
40 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range
Z Package
−65°C to +175°C
P, S Packages
−65°C to +150°C
Operating Temperature Range
OP297E (Z)
−40°C to +85°C
OP297F, OP297G (P, S)
−40°C to +85°C
Junction Temperature
Z Package
−65°C to +175°C
P, S Packages
−65°C to +150°C
Lead Temperature
(Soldering, 60 sec)
300°C
1 For supply voltages less than ±20 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for worst-case mounting conditions, that is, θJA
is specified for device in socket for CERDIP and PDIP pack-
ages; θJA is specified for device soldered to printed circuit board
for the SOIC package.
Table 4. Thermal Resistance
Package Type
θJA
θJC
8-Lead CERDIP (Z-Suffix)
134
12
8-Lead PDIP (P-Suffix)
96
37
8-Lead SOIC (S-Suffix)
150
41
Unit
°C/W
°C/W
°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
–
1/2
OP297
+
V1 20V p-p @ 10Hz
2kΩ
50kΩ
50Ω
–
1/2
OP297
V2
+
CHANNEL SEPARATION = 20 log
V1
V2/10000
Figure 4. Channel Separation Test Circuit
Rev. F | Page 4 of 16