EVAL-SSM2301_15 Datasheet, PDF (4/8 Pages) Analog Devices – Evaluation Board for Filterless Class-D Audio Amplifier

EVAL-SSM2301
LAYOUT GUIDELINES
1. Place at least nine vias on the solder pad for the thermal
pad of the amplifier for proper conduction of heat to the
opposite side of the board. The outer diameter of the vias
should be 0.5 mm and the inner diameter should be 0.25 mm
to 0.3 mm. Use a PCB area of at least 2 cm² equivalent area
on the opposite side of the layer of the amplifier chip as a
heat sink. Also, extend the ground pad (for the thermal
pad) as much as possible on the amplifier side of the PCB
as a heat sink (see Figure 4). If internal layers are available,
allocate a certain area as a heat sink; make sure to connect the
vias conducting the heat to the internal layers.
TOP LAYER
INTERNAL
AND/OR
BOTTOM LAYER
Figure 4. Heat Sink Layout
2. Place the EMI filtering beads, B1, B2 and B3, as close to the
amplifier chip as possible.
3. Place the decoupling capacitors for the beads, C8, C9, and
C12, as close to the amplifier chip as possible, and connect
all their ground terminals together as close as possible.
Ideally, solder their ground terminals together, as shown in
Figure 5; do not rely on PCB tracks or ground planes for
connecting their ground terminals together.
SMALL
INDUCTOR
C8
COPPER
FILL
INPUT
TRACK
C10
C13
OUTPUT
TRACK
C11
C12 C9
Figure 5. Placement and Routing for Decoupling Capacitors
4. The 1 nF capacitor and the ferrite bead can block the EMI
for up to 250 MHz. To eliminate EMI higher than 250 MHz,
place a low value small size capacitor, such as a 100 pF, 0402
size capacitor, in parallel with the 1 nF decoupling capacitor.
Place this small capacitor a short distance away from the
1 nF capacitor and use the PCB connection track as an
inductor to form a PI shape low-pass filter, as shown in
Figure 5.
5. If implementing a PCB track PI filter, the arriving input
PCB track and the leaving output PCB track connection to
the decoupling capacitor should not be connected. The
correct layout example is shown in Figure 5. The incorrect
layout is shown in Figure 6.
6. Decouple the input port nodes with small capacitors, such
as a 100 pF C3 and a 100 pF C4. They are not necessary but
can lower the input EMI.
C8
C12 C9
C10
INPUT OUTPUT
C13
TRACK TRACK
C11
Figure 6. Wrong Routing for the Inductive Track Output Decoupling
Capacitor
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