EVAL-AD7719-EB Datasheet, PDF (4/21 Pages) Analog Devices – Evaluation Board for the AD7719, 16&24-Bit, Dual Sigma Delta ADC

EVAL-AD7719-EB
18
1
4
CS
5
SCLK
6
SYNC
7-8
NC
9
DV_DD
10
RDY
11-12
13
NC
DOUT
14-18
19-30
31-36
NC
DGND
NC
36
19
Fig. 3: 36-way Centronics (SKT2) Pin Configuration
Chip Select. The signal on this pin is buffered before being applied to the CS pin of the
AD7719. CS is an active low Logic Input used to select the AD7719. With this input hard-
wired low, the AD7719 can operate in its three-wire interface mode with SCLK, DIN and DOUT
used to interface to the device. CS can be used to select the device in systems with more than
one device on the serial bus or as a frame synchronization signal in communicating with the
AD7719.
Serial Clock. The signal on this pin is buffered before being applied to the SCLK pin of the
AD7719. An external serial clock is applied to this input to read/write serial data from/to the
AD7719. This serial clock can be continuous with all data transmitted in a continuous train
of pulses. Alternatively, it can be non-continuous with the information being transmitted to
the AD7719 in smaller batches of data.
Logic Input. The signal on this pin is buffered before being applied to the SYNC pin of the
AD7719. The SYNC input allows for synchronisation of the digital filters and modulators
across a number of AD7719s. While SYNC is low, the nodes of the digital filter, the filter
control logic and the calibration control logic are held in a reset state.
No Connect. These pins are not connected on the evaluation board.
Digital Supply Voltage. This provides the supply voltage for the buffer chips, U3-U5,
which buffer the signals between the AD7719 and J1/J4.
Logic output. This is a buffered version of the signal on the AD7719 RDY pin. A logic low
on this output indicates that either the Main ADC or Auxiliary ADC has valid data in their
data register. The RDY pin will return high upon completion of a read operation of a full output
word. If data is not read RDY will return high prior to the next update indicating to the user
that a read operation should not be initiated. The RDY pin also returns low after the
completion of a calibration cycle. The RDY pin is effectively the NOR of the RDY0 and RDY1
bits in the Status register. If one of the ADCs is disabled the RDY pin reflects the active ADC.
RDY does not return high aftera calibration until the mode bits are written to enabling a new
conversion or calibration.
No Connect. These pins are not connected on the evaluation board.
Serial Data Output. This is a buffered version of the signal on the AD7719 DOUT pin. Serial
Data Output with serial data obtained from the output shift register on the AD7719. The output
shift register can contain information from of the on-chip registers depending on the register
selection bits of the Communications Register.
No Connect. These pins are not connected on the evaluation board.
Ground reference point for digital circuitry. Connects to the DGND plane on the evaluation
board.
No Connect. These pins are not connected on the evaluation board.
SOCKETS
There are eighteen sockets relevant to the operation of the AD7719 on this evaluation board. The functions of
these sockets are outlined in Table 4.
Table 4. Socket Functions
Socket
J4
Function
9-way D-Type connector used to interface to other systems.
-4-
Rev. B