EVAL-5CH6CHSOICEBZ Datasheet, PDF (4/8 Pages) Analog Devices – Access to all data channels

UG-936
EVAL-5CH6CHSOICEBZ User Guide
5. A populated 2-pin header to provide a signal ground pair
for use with clip leads or for temporarily shorting a channel
to ground.
6. Groupings of three open through holes consisting of a signal
and two ground connections. These holes can hardwire
signal wires into the PCB, install a header to accept an active
probe, or install a 2-pin header to allow adjacent channels to
temporarily be shorted together.
7. A 0805 pad layout between the signal and GNDx where a
load capacitor or pull-down resistor can be installed.
Figure 2 shows many of the optional components installed, as well
as how the jumpers can temporarily connect channels. Figure 2
also shows a signal connected to the first channel SMA, which is
then fanned out to the top three channels and monitored by an
active scope probe.
6 OPEN THROUGH HOLES
FOR ACTIVE PROBES
GND/GND/SIGNAL
2 TERMINATION
5 2 PIN HEADER
GND/SIGNAL
BYPASS CAPACITANCE ON THE PCB
Several positions and structures are provided to allow optimal
bypass capacitance for the DUT on the evaluation board.
Provisions are made for optional surface-mount bulk capacitors
to be installed near the power connectors to compensate for long
cables to the power supply. Bypass capacitors are installed near the
iCoupler data isolator and consist of a 0.1 µF capacitor for each
DUT VDDx pin on the top side of the evaluation board.
The PCB also implements a distributed capacitive bypass. This
bypass consists of power and ground planes closely spaced on
the inner layers of the PCB, which reduces noise and the
transmission of EMI without using complex design features.
HIGH VOLTAGE CAPABILITY
This PCB is designed in adherence with 2500 V basic insulation
practices. High voltage testing beyond 2500 V is not recommended.
Do not rely on the evaluation board for safety functions.
7 LOAD _{3 CONNECT TO SMA}
4 PULL-UP
1 SMA CONNECTOR PADS
NOTES
1. THE NUMBERED COMPONENTS IN THIS FIGURE CORRESPOND
TO THE DESCRIPTIONS IN THE DATA I/O STRUCTURES SECTION.
Figure 3. Configuration and Monitoring Structures
Rev. B | Page 4 of 8