DAC1423_15 Datasheet, PDF (4/6 Pages) Analog Devices – 4-20MA 10 BIT ISOLATED DIGITAL TO ANALOG CONVERTER

the loop supply is the most secure power source, since the
DAC1423 will remain operable even though the system has
failed, as long as the loop supply continues to operate.
"LOOP ^,6
-^{loUT .5mA}
The performance of the DAC1423 running in the sync mode
is essentially no different from the free running mode, except
that there may be slight offset and span shifts ("'"1LSB) if the
carrier frequency is pulled appreciably from its free running
frequency. In no case should the carrier frequency be pulled
more than :t15% from its nominal free running frequency.
DIGITAL INTERFACE (PARALLEL)
OUTPUT
COMMON
t:-,
.VSUPPLY
67
The parallel interface of the DAC1423 is a 5V CMOS design,
arranged to offer a great deal of interfacing flexibility to a
variety of user systems.
OAC1423
The interface consists of a lO-bit input latch, a 10-bit tri-
state output, and the associated control lines for read and
SUPPLY 164
COMMON
write operations. As shown in Figure 7, the 8 lower bits and
2 upper bits of both the latch and the tri-state are separately
controlled, allowing interfaces to both 8-bit and 16-bit bus
Figure 4. Operation with Isolated Loop and Power Supplies
architectures, For 10-bit or greater bus operation, the LO and
OB~ SOLETE DAC1423
"LOOP,6
.VSUPPLY' 67
DAC1423
RL
OUTPUT
COMMON
SUPPl Y 64
COMMON
Figure 5. Operation with Common Supply DAC1423
SYNCHRONIZATION
The DAC1423 contains an internal oscillator which generates
the carrier frequency for the modulation process. In most
cases, there is no appreciable leakage from this oscillator, and
it may be ignored by the user. However, when a DAC1423 is
HIGH write lines may be connected together, as well as the
LO and HIGH read lines,
TO
10 ^10BIT
CMOS
DAC
used in a system which contains a clock at or near this carrier
frequency, or when several DAC1423's are used adjacent to
one another, it is possible that a heterodyning phenomenon
can occur which results in beat notes that may (or may not)
fall within the system's passband. For this reason, the DAC1423
contains provisions for external or multiple synchronization.
Pin 68 is the SYNC IN pin which can be driven from an ex-
ternal clock. The external clock should be within 15% of free
running frequency of the DAC1423 (200kHz :t15%). It should
OIGITAL
COMMON
VDDOUT
NOTE, IN PARALLEL OPERATION, INCREMENTI
DECREMENT LINES ARE STILL ACTIVE.
Figure 7. DAC1423 Digital Interface Architecture
be a 5V CMOS level (50% duty cycle) via a 2200pF capacitor
in series with pin 68.
An example of an 8-bit microprocessor interface is shown in
If external sync is not used, leave the SYNC IN pin uncon-
nected; the DAC1423 will free run at approximately 200kHz.
Note that the SYNC IN signal is referred to power common,
not loop common or digital common.
Figure 8. In this case, the data is arranged as two bytes, right
justified. The digital inputs to the DAC1423 are CMOS, there-
fore, rigid logic levels are required. In some cases, double buf-
fering may be required for bus interface.
When multiple DAC1423 's are used, it is recommended that
their sync provisions be "daisy chained" as shown in Figure 6.
The SYNC OUT pin of one DAC1423 is used as the external
sync drive for the next DAC1423. Note that the first DAC1423
in the chain may either "free run" or be synchronized from an
external source.
OAC1423
#1
OAC1423
#2
DAC1423
#3
:>-²²i⁰I^0p-^F
FROM EXTERNAL SYNC OR
lEFT OPEN, IN WHICH #1
BECOMES THE MASTER
SYNC GENERATOR
TO ADDITIONAL
OAC1423
Figure 6. Synchronizing Multiple DAC1423's
The ou tpu t drive capability of the tri-states is 1 TTL load; in
general, the DAC1423 may be used directly on most NMOS
or CMOS microcomputer buses if the 3.3V minimum logic
"1" level is observed. In some cases, pullups may be required.
In the event of computer failure, the bus inputs must go to
either a high or a low state, but read, write and clear lines
must go to a low state.
BUMPLESS TRANSFER
In process control applications, there will be times when the
computer power fails and critical controls must be operated
manually. To avoid causing a "bump" in the process, such as
commanding a manually closed valve to fully open when
switched to automatic control, it is essential that the com-
puter knows the exact condition of the system when it re-
sumes control. This is known as "bump less transfer".
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