ADuM1100 Datasheet, PDF (4/16 Pages) Analog Devices – iCoupler Digital Isolator

ADuM1100
ELECTRICAL
SPECIFICATIONS,
MIXED
5
V/3
V
or
3
V/5
V
OPERATION¹
(5 V/3 V operation: 4.5 V ≤ V_DD1
≤ 5.5 V, 3.0 V ≤ V_DD2 ≤ 3.6 V.
3 V/5 V operation: 3.0 V ≤ V_DD1 ≤ 3.6 V, 4.5 V ≤ V_DD2 ≤ 5.5 V. All min/max specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at T_A = 25؇C, V_DD1 = 3.3 V, V_DD2 = 5 V or V_DD1 = 5 V, V_DD2 = 3.3 V.)
Parameter
DC SPECIFICATIONS
Input Supply Current, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Input Supply Current, 25 Mbps
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current, 25 Mbps
5 V/3 V Operation
3 V/5 V Operation
Input Supply Current, 50 Mbps
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current, 50 Mbps
5 V/3 V Operation
3 V/5 V Operation
Input Currents
Logic High Output Voltage,
5 V/3 V Operation
Logic Low Output Voltage,
5 V/3 V Operation
Logic High Output Voltage,
3 V/5 V Operation
Logic Low Output Voltage,
3 V/5 V Operation
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width³
Maximum Data Rate⁴
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width³
Maximum Data Rate⁴
For All Grades
Propagation Delay Time to Logic
Low/High Output^{5, 6}
5 V/3 V Operation (See TPC 5)
3 V/5 V Operation (See TPC 6)
Pulse Width Distortion, |t_PLH – t_PHL|⁶
5 V/3 V Operation
3 V/5 V Operation
Change versus Temperature
5 V/3 V Operation
3 V/5 V Operation
Propagation Delay Skew
(Equal Temperature)^{6, 8}
5 V/3 V Operation
3 V/5 V Operation
Symbol Min
Typ Max Unit Test Conditions
I_DDI(Q)
I_DDO(Q)
I_DDI(25)
I_DDO(25)
I_DDI(50)
I_DDO(50)
I_IA
V_OH
V_OL
V_OH
V_OL
0.3 0.8 mA
0.1 0.3 mA
0.005 0.04 mA
0.01 0.06 mA
2.2 3.5 mA 12.5 MHz Logic Signal Frequency
2.0 2.8 mA 12.5 MHz Logic Signal Frequency
0.3 0.7 mA 12.5 MHz Logic Signal Frequency
0.5 1.0 mA 12.5 MHz Logic Signal Frequency
4.5 7.0 mA 25 MHz Logic Signal Frequency
4.0 6.0 mA 25 MHz Logic Signal Frequency
1.2 1.6 mA
1.0 1.5 mA
–10
+0.01 +10 µA
V_DD2 – 0.1 3.3
V_DD2 – 0.5 3.0
0.0
V
V
0.1 V
0.04 0.1 V
0.3 0.4 V
V_DD2 – 0.1 5.0
V_DD2 – 0.8 4.6
0.0
V
V
0.1 V
0.03 0.1 V
0.3 0.8 V
25 MHz Logic Signal Frequency
25 MHz Logic Signal Frequency
0 ≤ V_IA, V_IB, V_IC, V_ID ≤ V_DD1 or V_DD2
I_O = –20 µA, V_I = V_IH
I_O = –2.5 mA, V_I = V_IH
I_O = 20 µA, V_I = V_IL
I_O = 400 µA, V_I = V_IL
I_O = 2.5 mA, V_I = V_IL
I_O = –20 µA, V_I = V_IH
I_O = –4 mA, V_I = V_IH
I_O = 20 µA, V_I = V_IL
I_O = 400 µA, V_I = V_IL
I_O = 4 mA, V_I = V_IL
PW
25
PW
50
t_PHL, t_PLH
PWD
t_PSK1
40 ns C_L = 15 pF, CMOS Signal Levels
Mbps C_L = 15 pF, CMOS Signal Levels
20 ns C_L = 15 pF, CMOS Signal Levels
Mbps C_L = 15 pF, CMOS Signal Levels
13 21 ns C_L = 15 pF, CMOS Signal Levels
16 26 ns C_L = 15 pF, CMOS Signal Levels
0.5 2
0.5 3
ns C_L = 15 pF, CMOS Signal Levels
ns C_L = 15 pF, CMOS Signal Levels
3
ps/ºC C_L = 15 pF, CMOS Signal Levels
10
ps/ºC C_L = 15 pF, CMOS Signal Levels
12 ns C_L = 15 pF, CMOS Signal Levels
15 ns C_L = 15 pF, CMOS Signal Levels
–4–
REV. E