ADSP-2186BSTZ-133 Datasheet, PDF (4/36 Pages) Analog Devices – DSP Microcomputer

ADSP-2186
where pin functionality is reconfigurable, the default state is
shown in plain text; alternate functionality is shown in italics.
Common-Mode Pins
Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL0/
PF5
IRQL1/
PF6
# Input/
of Out-
Pins put Function
1I
Processor Reset Input
1I
Bus Request Input
1 O Bus Grant Output
1 O Bus Grant Hung Output
1 O Data Memory Select Output
1 O Program Memory Select Output
1 O Memory Select Output
1 O Byte Memory Select Output
1 O Combined Memory Select Output
1 O Memory Read Enable Output
1 O Memory Write Enable Output
1I
Edge- or Level-Sensitive
Interrupt Request¹
I/O Programmable I/O Pin
1I
Level-Sensitive Interrupt Requests¹
I/O Programmable I/O Pin
1I
Level-Sensitive Interrupt Requests¹
I/O Programmable I/O Pin
Memory Interface Pins
The ADSP-2186 processor can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running.
Full Memory Mode Pins (Mode C = 0)
#
of Input/
Pin Name Pins Output Function
A13:0
D23:0
14 O
24 I/O
Address Output Pins for Pro-
gram, Data, Byte and I/O Spaces
Data I/O Pins for Program,
Data, Byte and I/O Spaces
(8 MSBs Are Also Used as
Byte Memory Addresses)
Host Mode Pins (Mode C = 1)
#
of Input/
Pin Name Pins Output Function
IAD15:0 16 I/O
IDMA Port Address/Data Bus
IRQE/
PF4
1I
Edge-Sensitive Interrupt Requests¹
A0
I/O Programmable I/O Pin
1
O
Address Pin for External I/O,
Program, Data, or Byte Access
PF3
1 I/O Programmable I/O Pin
D23:8
16 I/O
Data I/O Pins for Program,
Mode C/
1
PF2
Mode B/
1
PF1
Mode A/
1
PF0
CLKIN, XTAL 2
I
Mode Select Input—Checked
only During RESET
I/O Programmable I/O Pin During
Normal Operation
I
Mode Select Input—Checked
only During RESET
I/O Programmable I/O Pin During
Normal Operation
I
Mode Select Input—Checked
only During RESET
I/O Programmable I/O Pin During
Normal Operation
I
Clock or Quartz Crystal Input
IWR
IRD
IAL
IS
IACK
1
I
1
I
1
I
1
I
1
O
Data Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS, and IOMS signals.
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
CLKOUT 1 O Processor Clock Output
Pin Terminations
SPORT0
5 I/O Serial Port I/O Pins
SPORT1
IRQ1:0
FI, FO
PWD
5 I/O Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out²
1I
Power-Down Control Input
PWDACK 1 O Power-Down Control Output
FL0, FL1, FL2 3 O Output Flags
V_DD
GND
6I
10 I
Power (LQFP)
Ground (LQFP)
V_DD
GND
11 I
20 I
Power (Mini-BGA)
Ground (Mini-BGA)
EZ-Port
9 I/O For Emulation Use
NOTES
1_{Interrupt/Flag pins retain both functions concurrently. If IMASK is set to}
enable the corresponding interrupts, the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices or
set as a programmable flag.
2_{SPORT configuration determined by the DSP System Control Register. Soft-}
ware configurable.
Pin
Name
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
D6 or
IRD
D5 or
IAL
I/O
3-State
(Z)
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
Reset
State
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z*
Caused
By
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
Unused
Configuration
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
–4–
REV. B