ADSP-2184L Datasheet, PDF (4/31 Pages) Analog Devices – DSP Microcomputer

ADSP-2184L
Common-Mode Pins
Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL0/
PF5
IRQL1/
PF6
IRQE/
PF4
# Input/
of Out-
Pins put Function
1I
Processor Reset Input
1I
Bus Request Input
1 O Bus Grant Output
1 O Bus Grant Hung Output
1 O Data Memory Select Output
1 O Program Memory Select Output
1 I/O Memory Select Output
1 O Byte Memory Select Output
1 O Combined Memory Select Output
1 O Memory Read Enable Output
1 O Memory Write Enable Output
1I
Edge- or Level-Sensitive
Interrupt Request¹
I/O Programmable I/O Pin
1I
Level-Sensitive Interrupt Requests¹
I/O Programmable I/O Pin
1I
Level-Sensitive Interrupt Requests¹
I/O Programmable I/O Pin
1I
Edge-Sensitive Interrupt Requests¹
I/O Programmable I/O Pin
PF3
1 I/O Programmable I/O Pin
Mode C/
PF2
1I
Mode Select Input—Checked
only During RESET
I/O Programmable I/O Pin During
Normal Operation
Mode B/
PF1
1I
Mode Select Input—Checked
only During RESET
I/O Programmable I/O Pin During
Normal Operation
Mode A/
PF0
1I
Mode Select Input—Checked
only During RESET
I/O Programmable I/O Pin During
Normal Operation
CLKIN, XTAL 2 I
Clock or Quartz Crystal Input
CLKOUT 1 O Processor Clock Output
SPORT0
5 I/O Serial Port I/O Pins
SPORT1
IRQ1:0/
FI, FO
PWD
5 I/O Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out²
1I
Power-Down Control Input
PWDACK 1 O Power-Down Control Output
FL0, FL1, FL2 3 O Output Flags
V_DD and GND 16 I
Power and Ground
EZ-Port
9 I/O For Emulation Use³
NOTES
1_{Interrupt/Flag pins retain both functions concurrently. If IMASK is set to}
enable the corresponding interrupts, the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices or
set as a programmable flag.
2_{SPORT configuration determined by the DSP System Control Register. Soft-}
ware configurable.
3_{See Designing an EZ-ICE-Compatible System in this data sheet for complete}
information.
Memory Interface Pins
The ADSP-2184L processor can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode, which
allows IDMA operation with limited external addressing capabili-
ties. The operating mode is determined by the state of the Mode C
pin during reset and cannot be changed while the processor is
running. (See Table VI for complete mode operation descriptions.)
Full Memory Mode Pins (Mode C = 0)
#
of
Pin Name Pins
Input/
Output Function
A13:0
D23:0
14 O
24 I/O
Address Output Pins for Pro-
gram, Data, Byte and I/O Spaces
Data I/O Pins for Program,
Data, Byte and I/O Spaces
(8 MSBs Are Also Used as
Byte Memory Addresses)
Host Mode Pins (Mode C = 1)
#
of
Pin Name Pins
Input/
Output Function
IAD15:0 16 I/O
A0
1
O
D23:8
IWR
IRD
IAL
IS
IACK
16 I/O
1
I
1
I
1
I
1
I
1
O
IDMA Port Address/Data Bus
Address Pin for External I/O,
Program, Data or Byte Access
Data I/O Pins for Program,
Data Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge
In Host Mode, external peripheral addresses can be decoded using the A0,
BMS, CMS, PMS, DMS and IOMS signals.
Setting Memory Mode
Memory Mode selection for the ADSP-2184L is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are passive and active.
Passive configuration involves the use of a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor’s
output driver. For minimum power consumption during
power-down, reconfigure PF2 to be an input, as the pull-up or
pull-down will hold the pin in a known state, and will not switch.
Active configuration involves the use of a three-stateable exter-
nal driver connected to the Mode C pin. A driver’s output en-
able should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). After
RESET is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output.
–4–
REV. 0