AD9837 Datasheet, PDF (4/28 Pages) Analog Devices – Low Power, 8.5 mW, 2.3 V to 5.5 V, Programmable Waveform Generator

AD9837
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter¹
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Limit at TMIN to TMAX
62.5
25
25
25
10
10
5
10
t4 − 5
5
3
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
Description
MCLK period (fMCLK = 16 MHz)
MCLK high duration (fMCLK = 16 MHz)
MCLK low duration (fMCLK = 16 MHz)
SCLK period
SCLK high duration
SCLK low duration
FSYNC to SCLK falling edge setup time
SCLK falling edge to FSYNC rising edge time
Data setup time
Data hold time
SCLK high to FSYNC falling edge setup time
1 _{Guaranteed by design; not production tested.}
Timing Diagrams
t₁
MCLK
t₂
t₃
Figure 2. Master Clock
t₁₁
SCLK
FSYNC
SDATA
t₅
t₄
t₇
t₆
t₈
D15
D14
t₁₀
t₉
D2
D1
D0
Figure 3. Serial Timing
D15
D14
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