AD9780_15 Datasheet, PDF (4/32 Pages) Analog Devices – Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs

AD9780/AD9781/AD9783
Data Sheet
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
DAC CLOCK INPUT (CLKP, CLKN)
Differential Peak-to-Peak Voltage (CLKP − CLKN)
Common-Mode Voltage
Maximum Clock Rate
DAC CLOCK TO ANALOG OUTPUT DATA LATENCY
SERIAL PERIPHERAL INTERFACE (CMOS INTERFACE)
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup time, SDI to SCLK (tDS)
Hold Time , SDI to to SCLK (tDH)
Data Valid ,SDO to SCLK, (tDV)
Setup time, CSB to SCLK (tDCSB)
SERIAL PERIPHERAL INTERFACE LOGIC LEVELS
Input Logic High
Input Logic Low
DIGITAL INPUT DATA (LVDS INTERFACE)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH to VIDTHL
Input Differential Input Impedance, RIN
Maximum LVDS Input Rate (per DAC)
Min
Typ
Max
400
800
1600
300
400
500
500
7
40
12.5
12.5
2.0
0.2
2.3
1.4
2.0
0.8
800
−100
20
80
500
1600
+100
120
Unit
mV
mV
MSPS
Cycles
MHz
ns
ns
ns
ns
ns
ns
V
V
mV
mV
mV
Ω
MSPS
Rev. B | Page 4 of 32