AD9501 Datasheet, PDF (4/12 Pages) Analog Devices – Digitally Programmable Delay Generator

AD9501
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12-19
20
AD9501 PIN DESCRIPTIONS
Name
Function
+V_S
LATCH
Positive voltage supply; nominally +5 V.
TTL/CMOS register control line. Logic HIGH latches input data D₀–D₇. Register is
transparent for logic LOW.
TRIGGER
TTL/CMOS-compatible input. Rising edge triggers the internal ramp generator, and begins
the delay cycle.
RESET
TTL/CMOS-compatible input. Logic HIGH resets the ramp voltage and OUTPUT.
DAC OUTPUT Output voltage of the internal digital-to-analog converter.
C_EXT
Optional external capacitor connected to +V_S; used with R_SET and 8.5 pF internal capacitor
to determine full-scale delay range (t_DFS).
R_SET
External resistor to ground, used to determine full-scale delay range (t_DFS).
OFFSET ADJUST Normally connected to GROUND. Can be used to adjust minimum propagation delay (t_PD);
see Theory of Operation text.
GROUND
Circuit ground return.
OUTPUT
TTL-compatible delayed output pulse.
+V_S
D₀–D₇
GROUND
Positive voltage supply; nominally +5 V.
TTL/CMOS-compatible inputs, used to set the programmed delay of the AD9501 delayed
output. D₀ is LSB and D₇ is MSB.
Circuit ground return.
AD9501 Equivalent Circuits
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9501 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A