AD9410_15 Datasheet, PDF (4/20 Pages) Analog Devices – 10-Bit, 210 MSPS ADC

AD9410
SWITCHING SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 2.
Parameter
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Clock Pulse Width High, tEH
Clock Pulse Width Low, tEL
Aperture Delay, tA
Aperture Uncertainty (Jitter)
Output Valid Time, tV
Output Propagation Delay, tPD
Output Rise Time, tR
Output Fall Time, tF
CLKOUT Propagation Delay, tCPD1
Data to DCO Skew, (tPD – tCPD)
DS Setup Time, tSDS
DS Hold Time, tHDS
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)
Temp
Full
Full
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Test Level
VI
IV
IV
IV
V
V
VI
VI
V
V
VI
IV
IV
IV
VI
VI
Min Typ
210
1.2
2.4
1.2
2.4
1.0
0.65
3.0
1.8
1.4
2.6
4.8
0
1
0.5
0
A = 6, B = 6
A = 7, B = 6
Max Unit
MSPS
100
MSPS
ns
ns
ns
ps rms
ns
7.4
ns
ns
ns
6.4
ns
2
ns
ns
ns
Cycles
Cycles
1 _{CLOAD = 5 pF.}
DIGITAL SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 3.
Parameter
Temp Test Level Min
Typ Max
Unit
DIGITAL INPUTS
DFS, Input Logic 1 Voltage
Full IV
4
V
DFS, Input Logic 0 Voltage
Full IV
1
V
DFS, Input Logic 1 Current
Full V
50
μA
DFS, Input Logic 0 Current
Full V
50
μA
I/P Input Logic 1 Current¹
Full V
400
μA
I/P Input Logic 0 Current¹
Full V
1
μA
CLK+, CLK− Differential Input Voltage
Full IV
0.4
V
CLK+, CLK− Differential Input Resistance
Full V
1.6
kΩ
CLK+, CLK− Common-Mode Input Voltage²
Full V
1.5
V
DS, DS Differential Input Voltage
Full IV
0.4
V
DS, DS Common-Mode Input Voltage
Full V
1.5
V
Digital Input Pin Capacitance
25°C V
3
pF
DIGITAL OUTPUTS
Logic 1 Voltage (VDD = 3.3 V)
Logic 0 Voltage (VDD = 3.3 V)
Output Coding
Full VI
VDD – 0.05
V
Full VI
0.05
V
Binary or Twos Complement
1 _{I/P pin Logic 1 = 5 V, Logic 0 = GND. It is recommended to use a series 2.5 kΩ (±10%) resistor to VDD when setting to Logic 1 to limit input current.}
2 _{See Clock Input section.}
Rev. A | Page 4 of 20