AD7869_15 Datasheet, PDF (4/16 Pages) Analog Devices – LC MOS Complete, 14-Bit Analog I/O System

AD7869
TIMING SPECIFICATIONS^{1, 2} (V_DD = +5 V ؎ 5%, V_SS = –5 V ؎ 5%, AGND = DGND = 0 V)
Parameter
Limit at T_MIN, T_MAX
(All Versions)
Units
Conditions/Comments
ADC TIMING
t₁
t₂₃
t₃
t₄
t₅₄
t₆
t₁₃₅
50
440
100
20
100
155
4
100
2 RCLK + 200 to
3 RCLK + 200
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns typ
CONVST Pulse Width
RCLK Cycle Time, Internal Clock
RFS to RCLK Falling Edge Setup Time
RCLK Rising Edge to RFS
RCLK to Valid Data Delay, C_L = 35 pF
Bus Relinquish Time after RCLK
CONVST to RFS Delay
DAC TIMING
t₇
50
t₈
75
t₉
150
t₁₀
30
t₁₁
75
t_l2
40
ns min
ns min
ns min
ns min
ns min
ns min
TFS to TCLK Falling Edge
TCLK Falling Edge to TFS
TCLK Cycle Time
Data Valid to TCLK Setup Time
Data Valid to TCLK Hold Time
LDAC Pulse Width
NOTES
1_{Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a}
voltage level of 1.6 V.
2_{Serial timing is measured with a 4.7 kΩ pull-up resistor on DR and RFS and a 2 kΩ pull-up resistor on RCLK. The capacitance on all three outputs is 35 pF.}
3_{When using internal clock, RCLK mark/space ratio (measured form a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space}
ratio = external clock mark/space ratio.
4_{DR will drive higher capacitance loads but this will add to t5 since it increases the external RC time constant (4.7 kΩ//CL) and hence the time to reach 2.4 V.}
5_{Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.}
6_{TCLK mark/space ratio is 40/60 to 60/40.}
ABSOLUTE MAXIMUM RATINGS*
(T_A = + 25°C unless otherwise noted)
V_DD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V_SS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V_DD + 0.3 V
V_OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . V_SS to V_DD
V_IN to AGND . . . . . . . . . . . . . . . . V_SS –0.3 V to V_DD + 0.3 V
RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to V_DD + 0.3 V
RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V_DD + 0.3 V
RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V_DD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V_DD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to V_DD + 0.3 V
Operating Temperature Range
J Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
A Version . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7869 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B