AD5627R_07 Datasheet, PDF (4/32 Pages) Analog Devices – Dual, 12-/14-/16-Bit nanoDACs® with 5 ppm/°C On-Chip Reference, I2C® Interface

AD5627R/AD5647R/AD5667R, AD5627/AD5667
Parameter
LOGIC INPUTS (ADDR, CLR, LDAC)³
IIN, Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
VHYST, Input Hysteresis
LOGIC INPUTS (SDA, SCL)
IIN, Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
VHYST, Input Hysteresis
LOGIC OUTPUTS (OPEN-DRAIN)
VOL, Output Low Voltage
Floating-State Leakage Current
Floating-State Output Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)⁴
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)⁵
Min
Typ Max
Unit
0.85 × VDD
2
20
0.1 × VDD
±1
μA
0.15 × VDD V
V
pF
pF
V
0.7 × VDD
2
0.1 × VDD
±1
μA
0.3 × VDD V
V
pF
V
0.4
V
0.6
V
±1
μA
2
pF
2.7
5.5
V
0.4 0.5
mA
0.35 0.45
mA
0.95 1.15
mA
0.8 0.95
mA
0.48 1
μA
Conditions/Comments¹
ADDR
CLR, LDAC
ISINK = 3 mA
ISINK = 6 mA
VIH = VDD, VIL = GND
Internal reference off
Internal reference off
Internal reference on
Internal reference on
VIH = VDD, VIL = GND
1 _{Temperature range: B grade: −40°C to +105°C.}
2 _{Linearity calculated using a reduced code range: AD5567R/AD5667 (Code 512 to Code 65,024); AD5647R (Code 128 to Code 16,256); AD5627R/AD5627 (Code 32 to}
Code 4064). Output unloaded.
3 _{Guaranteed by design and characterization, not production tested.}
4 _{Interface inactive. All DACs active. DAC outputs unloaded.}
5 _{All DACs powered down.}
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