AD5453_15 Datasheet, PDF (4/28 Pages) Analog Devices – 8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface

AD5450/AD5451/AD5452/AD5453
Parameter
Min
Typ
Max
DYNAMIC PERFORMANCE¹
Reference-Multiplying BW
12
Multiplying Feedthrough Error
72
64
44
Output Voltage Settling Time
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
10% to 90% Settling Time
Digital-to-Analog Glitch Impulse
Output Capacitance
IOUT1
IOUT2
Digital Feedthrough
100
110
24
40
16
33
20
40
10
30
2
13
28
18
5
0.5
Analog THD
83
Digital THD
50 kHz fOUT
71
20 kHz fOUT
77
Output Noise Spectral Density
25
SFDR Performance (Wide Band)
50 kHz fOUT
78
20 kHz fOUT
74
SFDR Performance (Narrow Band)
50 kHz fOUT
87
20 kHz fOUT
85
Intermodulation Distortion
79
POWER REQUIREMENTS
Power Supply Range
2.5
5.5
IDD
0.4
10
0.6
Power Supply Sensitivity¹
0.001
1 _{Guaranteed by design and characterization, not subject to production test.}
Unit
MHz
dB
dB
dB
ns
ns
ns
ns
ns
nV-s
pF
pF
pF
pF
nV-s
dB
dB
dB
nV/√Hz
dB
dB
dB
dB
dB
V
µA
µA
%/%
Data Sheet
Test Conditions
VREF = ±3.5 V, DAC loaded with all 1s
VREF = ±3.5 V, DAC loaded with all 0s
100 kHz
1 MHz
10 MHz
VREF = 10 V, RLOAD = 100 Ω; DAC latch alternately
loaded with 0s and 1s
Interface delay time
Rise and fall times, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, VREF = 0 V
DAC latches loaded with all 0s
DAC latches loaded with all 1s
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz
Clock = 1 MHz, VREF = 3.5 V
@ 1 kHz
Clock = 1 MHz, VREF = 3.5 V
Clock = 1 MHz, VREF = 3.5 V
f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V
TA = −40°C to +125°C, logic inputs = 0 V or VDD
TA = 25°C, logic inputs = 0 V or VDD
∆VDD = ±5%
Rev. G | Page 4 of 28