AD5444YRM-REEL Datasheet, PDF (4/28 Pages) Analog Devices – 12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface

AD5444/AD5446
Data Sheet
Parameter
Min
Typ Max Unit
DYNAMIC PERFORMANCE¹
Reference Multiplying Bandwidth
12
MHz
Multiplying Feedthrough Error
72
dB
64
dB
44
dB
Output Voltage Settling Time
Measured to ±1 mV of FS
Measured to ±4 mV of FS
Measured to ±16 mV of FS
Digital Delay
10%-to-90% Settling Time
Digital-to-Analog Glitch Impulse
Output Capacitance
IOUT1
IOUT2
Digital Feedthrough
100 110
ns
24
40
ns
16
33
ns
20
40
ns
10
30
ns
2
nV-s
13
pF
28
pF
18
pF
5
pF
0.5
nV-s
Analog THD
Digital THD
50 kHz fOUT
20 kHz fOUT
Output Noise Spectral Density
SFDR Performance (Wide Band)
50 kHz fOUT
20 kHz fOUT
SFDR Performance (Narrow Band)
50 kHz fOUT
20 kHz fOUT
Intermodulation Distortion
POWER REQUIREMENTS
Power Supply Range, VDD
2.5
Supply Current, IDD
Power Supply Sensitivity¹
83
71
77
25
78
74
87
85
79
5.5
0.4 10
0.6
0.001
1 _{Guaranteed by design and characterization; not subject to production test.}
dB
dB
dB
nV/√Hz
dB
dB
dB
dB
dB
V
µA
µA
%/%
Conditions
VREF = ±3.5 V, DAC loaded with all 1s
VREF = ±3.5 V, DAC loaded with all 0s
100 kHz
1 MHz
10 MHz
VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately
loaded with 0s and 1s
Interface delay time
Rise and fall time, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, VREF = 0 V
DAC latches loaded with all 0s
DAC latches loaded with all 1s
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz
Clock = 1 MHz, VREF = 3.5 V
@ 1 kHz
Clock = 10 MHz, VREF = 3.5 V
Clock = 1 MHz, VREF = 3.5 V
f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V
TA = −40°C to +125°C, logic inputs = 0 V or VDD
TA = 25°C, logic inputs = 0 V or VDD
∆VDD = ±5%
Rev. E | Page 4 of 28