AD5440 Datasheet, PDF (4/32 Pages) Analog Devices – Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface

AD5428/AD5440/AD5447
Parameter
Min
Multiplying Feedthrough Error
Output Capacitance
Digital Feedthrough
Output Noise Spectral Density
Analog THD
Digital THD
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Wide Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
100 kHz fOUT
50k Hz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50 kHz fOUT
Intermodulation Distortion
f1 = 40 kHz, f2 = 50 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
2.5
IDD
Power Supply Sensitivity
1 _{Guaranteed by design, not subject to production test.}
Typ Max Unit
70
dB
48
dB
12
17
pF
25
30
pF
1
nV-sec
25
nV/√Hz
81
dB
61
dB
66
dB
55
dB
63
dB
65
dB
50
dB
60
dB
62
dB
73
dB
80
dB
87
dB
70
dB
75
dB
80
dB
72
dB
65
dB
5.5
V
0.7
μA
0.5
10
μA
0.001 %/%
Data Sheet
Conditions
DAC latches loaded with all 0s, VREF = ±3.5 V
1 MHz
10 MHz
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
@ 1 kHz
VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz
Clock = 10 MHz, VREF = 3.5 V
AD5447, 65k codes, VREF = 3.5 V
AD5447, 65k codes, VREF = 3.5 V
AD5447, 65k codes, VREF = 3.5 V
Clock = 10 MHz
Clock = 25 MHz
TA = 25°C, logic inputs = 0 V or VDD
TA = −40°C to +125°C, logic inputs = 0 V or VDD
∆VDD = ±5%
Rev. C | Page 4 of 32