AD5320_05 Datasheet, PDF (4/20 Pages) Analog Devices – 2.7 V to 5.5 V, 140 μA, Rail-to-Rail Output 12-Bit DAC in an SOT-23

AD5320
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter^{1, 2}
t1 ³
t2
t3
t4
t5
t6
t7
t8
Limit at TMIN, TMAX
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
50
33
13
13
22.5
13
0
0
5
5
4.5
4.5
0
0
50
33
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK rising edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
1 _{All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.}
2 _{See Figure 2.}
3 _{Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.}
SCLK
SYNC
DIN
t₁
t₄
t₈
t₃
t₂
t₇
t₅
t₆
DB15
DB0
Figure 2. Serial Write Operation
Rev. C | Page 4 of 20