AD5306_15 Datasheet, PDF (4/24 Pages) Analog Devices – 2.5 V to 5.5 V, 400 A, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs

AD5306/AD5316/AD5326
Parameter ²
Short-Circuit Current
Power-Up Time
LOGIC INPUTS
(Excluding SCL, SDA)⁶
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
A Version¹
B Version¹
Min
Typ
Max
Min
Typ
Max
Unit
25
25
mA
16
16
mA
2.5
2.5
μs
5
5
μs
±1
±1
μA
0.8
0.8
V
0.6
0.6
V
0.5
0.5
V
1.7
1.7
V
Pin Capacitance
LOGIC INPUTS (SCL, SDA)⁶
VIH, Input High Voltage
VIL, Input Low Voltage
IIN, Input Leakage Current
VHYST, Input Hysteresis
CIN, Input Capacitance
Glitch Rejection
3
0.7 VDD
−0.3
0.05 VDD
8
3
VDD + 0.3 0.7 VDD
+0.3 VDD −0.3
±1
0.05 VDD
8
50
pF
VDD + 0.3 V
+0.3 VDD V
±1
μA
V
pF
50
ns
LOGIC OUTPUT (SDA)⁶
VOL, Output Low Voltage
Three-State Leakage Current
Three-State Output
8
Capacitance
POWER REQUIREMENTS
VDD
2.5
IDD (Normal Mode)⁸
VDD = 4.5 V to 5.5 V
500
0.4
0.6
±1
8
5.5
2.5
900
500
0.4
V
0.6
V
±1
μA
pF
5.5
V
900
μA
VDD = 2.5 V to 3.6 V
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
400
750
0.3
1
0.09
1
400
750
μA
0.3
1
μA
0.09
1
μA
Conditions/Comments
VDD = 5 V.
VDD = 3 V.
Coming out of power-
down mode; VDD = 5 V.
Coming out of power-
down mode; VDD = 3 V.
VDD = 5 V ± 10%.
VDD = 3 V ± 10%.
VDD = 2.5 V.
VDD = 2.5 V to 5.5 V;
TTL and 1.8 V CMOS
compatible.
SMBus compatible at
VDD < 3.6 V.
SMBus compatible at
VDD < 3.6 V.
See Figure 20.
Input filtering suppresses
noise spikes of less than
50 ns.
ISINK = 3 mA.
ISINK = 6 mA.
VIH = VDD and VIL = GND;
interface inactive.
All DACs in unbuffered
mode.
Buffered mode, extra
current is typically x mA
per DAC, where
x = 5 μA + VREF/RDAC.
VIH = VDD and VIL = GND;
interface inactive.
IDD = 3 μA (max) during
readback on SDA.
IDD = 1.5 μA (max) during
readback on SDA.
1 _{Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.}
2 _{See the Terminology section.}
3 _{DC specifications tested with the outputs unloaded.}
4 _{Linearity is tested using a reduced code range: AD5306 (Code 8 to 255); AD5316 (Code 28 to 1023); AD5326 (Code 115 to 4095).}
5 _{This corresponds to x codes. x = deadband voltage/LSB size.}
6 _{Guaranteed by design and characterization; not production tested.}
7 _{For the amplifier output to reach its minimum voltage, the offset error must be negative; for the amplifier output to reach its maximum voltage, VREF = VDD,}
the offset plus gain error must be positive.
8 _{Interface inactive; all DACs active. DAC outputs unloaded.}
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