AD1836_15 Datasheet, PDF (4/18 Pages) Analog Devices – Multichannel 96 kHz Codec

PRELIMINARY TECHNICAL DATA
AD1836–SPECIFICATIONS
TIMING (continued)
Parameter
ADC Serial Port
Normal Modes
t_ABH
ABCLK Delay High
Min
Max
Unit
max
ns
t_ABL
ABCLK Delay Low
max
ns
t_ALS
t_ABDD
t_ALRDD
LRCLK Delay
ASDATA Delay
ASDATA Delay
Packed 128, 256 Modes
t_ABH
ABCLK Delay High
max
ns
max
ns
max
ns
max
ns
t_ABL
ABCLK Delay Low
max
ns
t_ALS
t_ABDD
t_ALRDD
LRCLK Delay
ASDATA Delay
ASDATA Delay
TDM PACKED AUX, MASTER MODE
t_ABH
ABCLK Delay High
max
ns
max
ns
max
ns
max
ns
t_ABL
ABCLK Delay Low
max
ns
t_XBH
AUXBCLK Delay High
max
ns
t_XBL
AUXBCLK Delay Low
max
ns
t_ALS
t_XLS
t_ABDD
t_ALRDD
t_DDS
t_DDH
t_DDS
t_DDH
t_DXDD
t_DXDD
LRCLK Delay
AUXLRCLK Delay
ASDATA Delay
ASDATA Delay
AAUXDATA Setup
AAUXDATA Hold
DSDATA Setup
DSDATA Hold
DAUXDATA Delay
DAUXDATA Delay
max
ns
max
ns
max
ns
max
ns
min
ns
min
ns
min
ns
min
ns
max
ns
max
ns
Comments
From MCLK Rising
256 × f_S
512 × f_S
768 × f_S
From MCLK Rising
256 × f_S
512 × f_S
768 × f_S
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
From MCLK Rising
256 × f_S
512 × f_S
768 × f_S
From MCLK Rising
256× f_S
512 × f_S
768 × f_S
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
From MCLK Rising
256 × f_S
512 × f_S
768 × f_S
From MCLK Rising
256 × f_S
512 × f_S
768 × f_S
From MCLK Rising
256 × f_S
512 × f_S
768 × f_S
From MCLK Rising
256 × f_S
512 × f_S
768 × f_S
From ABCLK Falling
From ABCLK Falling
From ABCLK Falling
From ALRCLK Changing
(Left-Justified)
To AUXBCLK Rising
From AUXBCLK Rising
To DBCLK Rising
From DBCLK Rising
From AUXBCLK Falling
From AUXLRCLK Changing
(Left-Justified)
–4–
REV. PrC