ADUC7030 Datasheet, PDF (39/150 Pages) Analog Devices – Integrated Precision Battery Sensor For Automotive

Preliminary Technical Data
CODE EXECUTION TIME FROM SRAM AND
FLASH/EE
This chapter describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle as the
access time of the SRAM is 2ns and a clock cycle is 49ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM, or three cycle if the data is in Flash/EE, one
cycle to execute the instruction and two cycles to get the 32-bit
data from Flash/EE. A control flow instruction, for example a
branch instruction will take one cycle to fetch but also two
cycles to fill the pipeline with the new instructions.
Execution from Flash/EE
Because the Flash/EE width is 16-bit, execution from Flash/EE
cannot be done in one cycle, as from SRAM, when CD bit =0.
Also some dead time is needed before accessing data for any
value of CD bits.
In ARM mode, where instructions are 32 bits, two extra cycles
are needed to fetch any instruction when CD = 0 and in Thumb
mode, where instructions are 16 bits, one extra cycle is needed
to fetch any instruction.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the
instruction to be executed is a control flow instruction, an extra
cycle is needed to decode the new address of the program
counter and then four cycles are needed to fill the pipeline. A
ADuC7030/ADuC7033
data processing instruction involving only core register doesn’t
require any extra clock cycle but if it involves data in Flash/EE,
an extra clock cycle is needed to decode the address of the data
and two cycles to get the 32-bit data from Flash/EE. An extra
cycle must also be added before fetching another instruction.
Data transfer instruction are more complex and are
summarized Table 22.
Table 22. Typical execution cycles in ARM/Thumb mode
Instructions
Fetch
cycles
Dead
time
Data access
LD
2/1
1
2
LDH
2/1
1
1
LDM/PUSH
2/1
N
2×N
STR
2/1
1
2 × 50 µs
STRH
2/1
1
50µs
STRM/POP
2/1
N
2 × N × 50 µs
With 1 < N ≤ 16, N number of data to load or store in the
multiple load/store instruction.
By default, Flash/EE code execution will be suspended during
any Flash/EE erase or write cycle. A page (512 Bytes) erase cycle
takes 20 ms and a write (16 bits) word command takes 50μs.
However, the Flash/EE controller allows Erase/Write cycles to
be aborted, if the ARM core receives an enabled interrupt
during the current Flash/EE Erase/Write cycle. The ARM7 can
therefore immediately service the interrupt and then return to
repeat the Flash/EE command. The Abort operation will
typically take 10 clock cycles. If the abort operation is not
feasible, it is possible to run Flash/EE programming code and
the relevant interrupt routines from SRAM, allowing the core to
service the Interrupt immediately.
Rev. PrE | Page 39 of 150