ADSP-218XN_15 Datasheet, PDF (39/48 Pages) Analog Devices – DSP Microcomputer

ADSP-218xN
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
Parameter¹
Min
Max
Unit
Timing Requirements:
t_IKR
IACK Low Before Start of Read²
t_IRP
Duration of Read³
Switching Characteristics:
0
ns
10
ns
t_IKHR
IACK High After Start of Read²
t_IKDH
IAD15–0 Previous Data Hold After End of Read³
t_IKDD
IAD15–0 Previous Data Disabled After End of Read³
t_IRDE
IAD15–0 Previous Data Enabled After Start of Read
t_IRDV
IAD15–0 Previous Data Valid After Start of Read
10
ns
0
ns
10
ns
0
ns
10
ns
1 _{Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register}
or by an external host writing to the register. Disabled by default.
2 _{Start of Read = IS Low and IRD Low. Previous data remains until end of read.}
3 _{End of Read = IS High or IRD High.}
IACK
IS
t_{IK R}
t_{IK H R}
IRD
t_{IR P}
t_{IR D E}
IAD15–0
PR E V IO U S
DATA
t_{IR D V}
L EG EN D :
IM PL IES TH A T IS A N D IR D C A N B E
HELD INDEFINITELY BY HO ST
t_{IK D H}
t_{IK D D}
Figure 37. IDMA Read, Short Read Cycle in Short Read Only Mode
Rev. A | Page 39 of 48 | August 2006