ADE7569 Datasheet, PDF (39/136 Pages) Analog Devices – Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver

Preliminary Technical Data
ADE7566/ADE7569
Table 34. ACCMODE Register (0x0F)
Bit No. Mnemonic Default Description
7 to 6 Reserved 0
Reserved.
5
VARSIGN¹ 0
Configuration bit to select event that triggers a reactive power sign interrupt. If set to 0, VARSIGN
interrupt occurs when reactive power changes from positive to negative. If set to 1, VARSIGN interrupt
occurs when reactive power changes from negative to positive.
4
APSIGN
0
Configuration bit to select event that triggers an active power sign interrupt. If set to 0, APSIGN interrupt
occurs when active power changes from positive to negative. If set to 1, APSIGN interrupt occurs when
active power changes from negative to positive.
3
ABSVARM¹ 0
Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output.
2
SAVARM¹ 0
Logic 1 enables reactive power accumulation depending on the sign of the active power. If active power
is positive, VAR is accumulated as it is. If active power is negative, the sign of the VAR is reversed for the
accumulation. This accumulation mode affects both the VAR registers (VARHR, RVARHR, LVARHR) and the
pulse output when connected to VAR.¹
1
POAM
0
Logic 1 enables positive only accumulation of active power in energy register and pulse output.
0
ABSAM
0
Logic 1 enables absolute value accumulation of active power in energy register and pulse output.
1 _{This function is not available in the ADE7566 part.}
Table 35. GAIN Register (0x1B)
Bit No.
Mnemonic
7 to 5
PGA2[2:0]
Default
000
4
Reserved
0
3
CFSIGN_OPT
0
2 to 0
PGA1[2:0]
000
Description
These bits define the voltage channel input gain.
PGA2[2:0]
Result
000
Gain = 1
001
Gain = 2
010
Gain = 4
011
Gain = 8
100
Gain = 16
Reserved.
This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is
implemented.
CFSIGN_OPT Result
0
Filtered power signal
1
On a per CF pulse basis
These bits define the current channel input gain.
PGA1[2:0]
Result
000
Gain = 1
001
Gain = 2
010
Gain = 4
011
Gain = 8
100
Gain = 16
Table 36. Interrupt Status Register 1 SFR (MIRQSTL, 0xDC)
Bit No. Interrupt Flag Description
7
ADEIRQFLAG This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt are set. This bit is
automatically cleared when all of the enabled ADE status flags are cleared.
6-5
Reserved
Reserved.
4
VARSIGN¹
Logic 1 indicates that the reactive power sign has changed according to the configuration of ACCMODE register.
3
APSIGN
Logic 1 indicates that the active power sign has changed according to the configuration of ACCMODE register.
2
VANOLOAD Logic 1 indicates that an interrupt has been caused by apparent power no-load detected. This interrupt is also
used to reflect the part entering the Irms no load mode.
1
RNOLOAD¹
Logic 1 indicates that an interrupt has been caused by reactive power no-load detected.
0
APNOLOAD Logic 1 indicates that an interrupt has been caused by active power no-load detected.
1 _{This function is not available in the ADE7566 part.}
Rev. PrA | Page 39 of 136