AD9937 Datasheet, PDF (39/44 Pages) Analog Devices – CCD Signal Processor with Precision Timing™ Generator

AD9937
VDD
(INPUT) 1
INTERNAL
POWER-ON
AUTO-RESET
(LO-ACTIVE)
t_PWR1
2
VCKM
4
5
6
7
SERIAL
WRITES
OUTCONT
(REGISTER
CONTROLLED)
VD
(OUTPUT)
HD
(OUTPUT)
DIGITAL
OUTPUTS
V1A/B, V2, V3A/B, V4, TG1A, TG1B, TG3A, TG3B,
OFD, H1(A, B, C, D)
RS, H2(A, B), LM
1V
ODD FIELD
1H
EVEN FIELD
ODD FIELD
VCLK
t_SETTINGS2
t_DELAY3
NOTES
1_{THE INTERNAL POWER-ON AUTO RESET TIME tPWR = 1.0ms REGARDLESS OF THE VCLK CLOCK FREQUENCY.}
2_{IT TAKES 500␮s FOR VCLK TO SETTLE ONCE THE DIG_STBY REGISTER HAS BEEN PROGRAMMED.}
3_{IT TAKES FOUR VCKM CLOCK CYCLES FROM WHEN OUTCONT IS ASSERTED HIGH UNTIL THE VD, HD, AND DIGITAL OUTPUT DATA IS VALID.}
Figure 37. Recommended Power-Up Sequence
POWER-UP FOR MASTER MODE
When the AD9937 is powered up, the following sequence is
recommended. (Refer to Figure 37 for each step.)
1. Turn on power supplies for AD9937.
2. The internal power-on auto-reset circuit will deassert
1.0 ms after VDD settles. (All internal registers are reset to
the default values.)
3. The VCKM clock can be applied as soon as VDD settles.
4. Reset the internal AD9937 registers: write a 0x000000 to
the SW_RESET register (addr 0x00). This will set all inter-
nal register values to their default values. (This step is optional
because the internal power-on reset circuit is applied at
power-up.)
5. Write a 1 to the DIG_STBY and AFE_STBY registers
(addr 0x02). This will put the digital and analog circuits into
the normal operating mode.
6. Program all control, system, and mode registers.
7. Write a 1 to the OUTCONT_REG (addr 0x01). This will put
the digital outputs into the normal operating mode. The inter-
nal OUTCONT will be asserted high on the rising edge of the
32nd SCK clock when writing to the OUTCONT_REG.
Table XVIII. Start-Up Polarities
(While OUTCONT = LO)
Output
V1A/B
V2
V3A/B
V4
TG1A
TG1B
TG3A
TG3B
OFD
H1(A–D)
H2(A, B)
LM
RS
OUTCONT = LO
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
LO
REV. 0
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