AD7707_15 Datasheet, PDF (39/52 Pages) Analog Devices – 3-Channel 16-Bit, Sigma-Delta ADC

AD7707
MICROCOMPUTER/MICROPROCESSOR INTERFACING
The AD7707’s flexible serial interface allows for easy interface
to most microcomputers and microprocessors. The flowchart of
Figure 22 outlines the sequence that should be followed when
interfacing a microcontroller or microprocessor to the AD7707.
Figure 23 and Figure 24 show some typical interface circuits.
The serial interface on the AD7707 is capable of operating from
just three wires and is compatible with SPI interface protocols.
The 3-wire operation makes the part ideal for isolated systems in
which minimizing the number of interface lines also minimizes
the number of opto-isolators required in the system. The serial
clock input is a Schmitt-triggered input to accommodate slow
edges from optocouplers. The rise and fall times of other digital
inputs to the AD7707 should be no longer than 1 μs.
that require control of the CS input on the AD7707, one of the
port bits of the 68HC11 (such as PC1), which is configured as
an output, can be used to drive the CS input.
V_DD
V_DD
SS
AD7707
68HC11
RESET
SCK
MISO
MOSI
SCLK
DOUT
DIN
Most of the registers on the AD7707 are 8-bit registers, which
facilitates easy interfacing to the 8-bit serial ports of microcon-
trollers. The data register on the AD7707 is 16 bits, and the
zero-scale and full-scale calibration registers are 24-bit registers
but data transfers to these registers can consist of multiple 8-bit
transfers to the serial port of the microcontroller. DSP processors
and microprocessors generally transfer 16 bits of data in a serial
data operation. Some of these processors, such as the ADSP-2105,
have the facility to program the amount of cycles in a serial
transfer. This allows the user to tailor the number of bits in any
transfer to match the register length of the required register in
the AD7707.
Even though some of the registers on the AD7707 are only eight
bits in length, communicating with two of these registers in
successive write operations can be handled as a single 16-bit
data transfer if required. For example, if the setup register is to
be updated, the processor must first write to the communications
register (indicating that the next operation is a write to the
setup register) and then write eight bits to the setup register. If
required, this can all be performed in a single 16-bit transfer
because once the eight serial clocks of the write operation to the
communications register have been completed, the part
immediately sets itself up for a write operation to the setup
register.
CS
Figure 23. AD7707-to-68HC11 Interface
The 68HC11 is configured in master mode with its CPOL bit
set to a Logic 1 and its CPHA bit set to a Logic 1. When the
68HC11 is configured like this, its SCLK line idles high between
data transfers. The AD7707 is not capable of full duplex operation.
If the AD7707 is configured for a write operation, no data appears
on the DATA OUT lines even when the SCLK input is active.
Similarly, if the AD7707 is configured for a read operation, data
presented to the part on the DATA IN line is ignored even when
SCLK is active.
Coding for an interface between the 68HC11 and the AD7707 is
given in the C Code for Interfacing AD7707 to 68HC11 section.
In this example, the DRDY output line of the AD7707 is
connected to the PC0 port bit of the 68HC11 and is polled to
determine its status.
AD7707TO68HC11 INTERFACE
Figure 23 shows an interface between the AD7707 and the 68HC11
microcontroller. The diagram shows the minimum (3-wire)
interface with CS on the AD7707 hard-wired low. In this
scheme, the DRDY bit of the communications register is
monitored to determine when the data register is updated. An
alternative scheme, which increases the number of interface
lines to four, is to monitor the DRDY output line from the AD7707.
The monitoring of the DRDY line can be done in two ways. First,
DRDY can be connected to one of the 68HC11 port bits (such
as PC0), which is configured as an input. This port bit is then
polled to determine the status of DRDY. The second scheme is
to use an interrupt driven system, in which case the DRDY
output is connected to the IRQ input of the 68HC11. For interfaces
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