ADSP-21060 Datasheet, PDF (38/64 Pages) Analog Devices – ADSP-2106x SHARC DSP Microcomputer Family

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Link Ports —1 × CLK Speed Operation
Table 23. Link Ports—Receive
5V
3.3 V
Parameter
Min
Max
Min
Max
Timing Requirements
t_SLDCL
Data Setup Before LCLK Low¹
t_HLDCL
Data Hold After LCLK Low
t_LCLKIW
LCLK Period (1u Operation)
t_LCLKRWL
LCLK Width Low
t_LCLKRWH
LCLK Width High
Switching Characteristics
t_DLAHC
LACK High Delay After CLKIN High^{2, 3}
t_DLALC
LACK Low Delay After LCLK High
t_ENDLK
LACK Enable From CLKIN
t_TDLK
LACK Disable From CLKIN
3.5
3
t_CK
6
5
18 + DT/2
–3
5 + DT/2
3
3
t_CK
6
5
28.5 + DT/2
+13
20 + DT/2
18 + DT/2
–3
5 + DT/2
28.5 + DT/2
+13
20 + DT/2
1 _{For ADSP-21062, specification is 3 ns min.}
2 _{LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.}
3 _{For ADSP-21060C, specification is 18 + DT/2 ns min, 29 + DT/2 ns max.}
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 24. Link Ports—Transmit
5V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t_SLACH
LACK Setup Before LCLK High¹
18
18
ns
t_HLACH
LACK Hold After LCLK High
–7
–7
ns
Switching Characteristics
t_DLCLK
t_DLDCH
t_HLDCH
t_LCLKTWL
t_LCLKTWH
t_DLACLK
t_ENDLK
t_TDLK
Data Delay After CLKIN (1u
Operation)²
Data Delay After LCLK High³
Data Hold After LCLK High
LCLK Width Low⁴
LCLK Width High⁵
LCLK Low Delay After LACK High⁶
LACK Enable From CLKIN
LACK Disable From CLKIN
–3
(t_CK/2) – 2
(t_CK/2) – 2
(t_CK/2) + 8.5
5 + DT/2
15.5
15.5
ns
3
(t_CK/2) + 2
(t_CK/2) + 2
(3 u t_CK/2) + 17
20 + DT/2
–3
(t_CK/2) – 1
(t_CK/2) – 1.25
(t_CK/2) + 8
5 + DT/2
2.5
ns
ns
(t_CK/2) + 1.25
ns
(t_CK/2) + 1
ns
(3 u t_CK/2) + 17.5 ns
ns
20 + DT/2
ns
1 _{For ADSP-21060L/ADSP-21060LC, specification is 20 ns min.}
2 _{For ADSP-21060L, specification is 16.5 ns max; for ADSP-21060LC, specification is 16.75 ns max.}
3 _{For ADSP-21062, specification is 2.5 ns max.}
4 _{For ADSP-21062, specification is (tCK/2) – 1 ns min, (tCK/2) + 1.25 ns max; for ADSP-21062L, specification is (tCK/2) – 1 ns min, (tCK/2) + 1.5 ns max; for ADSP-21060LC}
specification is (t_CK/2) – 1 ns min, (t_CK/2) + 2.25 ns max.
5 _{For ADSP-21062, specification is (tCK/2) – 1.25 ns min, (tCK/2) + 1 ns max; for ADSP-21062L, specification is (tCK/2) – 1.5 ns min, (tCK/2) + 1 ns max; for ADSP-21060C}
specification is (t_CK/2) – 2.25 ns min, (t_CK/2) + 1 ns max.
6 _{For ADSP-21062, specification is (tCK/2) + 8.75 ns min, (3 × tCK/2) + 17 ns max; for ADSP-21062L, specification is (tCK/2) + 8 ns min, (3 × tCK/2) + 17 ns max; for}
ADSP-21060LC specification is (t_CK/2) + 8 ns min, (3 × t_CK/2) + 18.5 ns max.
Rev. F | Page 38 of 64 | March 2008