AD9979BCPZ Datasheet, PDF (38/56 Pages) Analog Devices – 14-Bit, CCD Signal Processor with Precision Timing Core

AD9979
Table 22. Standby Mode Operation
I/O Block
Total Shutdown (Default)^{1, 2}
AFE
Off
Timing Core
Off
H1
High-Z
H2
High-Z
H3
High-Z
H4
High-Z
HL
High-Z
RG
High-Z
DOUT
Low³
OUT_CONTROL = Low²
No change
No change
Low
High
Low
High
Low
Low
Low
Reference Standby
Only REFT, REFB on
On
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low
1 _{To exit total shutdown, write 00 to STANDBY (Address 0x00, Bits[1:0]), then reset the timing core after 100 μs to guarantee proper settling.}
2 _{Total shutdown mode takes priority over OUT_CONTROL for determining the output polarities.}
3 _{The status of the DOUT pins is unknown at power-up. Low status is guaranteed in total shutdown mode after the power-up sequence is completed.}
CIRCUIT CONFIGURATION
The AD9979 recommended circuit configurations are shown in
Figure 54 and Figure 55. Achieving good image quality from the
AD9979 requires careful attention to PCB layout. Route all signals
to maintain low noise performance. Directly route the CCD
output signal through a 0.1 μF capacitor to Pin 31. To minimize
interference with the CCDINM, CCDINP, REFT, and REFB
signals, carefully route the master clock (CLI) to Pin 28.
The H1 to H4, HL, and RG traces need low inductance to avoid
excessive distortion of the signals. Heavier traces are recommended
because of the large transient current demands on H1 to H4 and
HL from the capacitive load of the CCD. If possible, physically
locating the AD9979 closer to the CCD reduces the inductance
on these lines. Make the routing path as direct as possible from
the AD9979 to the CCD.
3 V System Compatibility
The AD9979 typical circuit connections for a 3 V system are
shown in Figure 54. This application uses an external 3.3 V
supply connected to the IOVDD input of the AD9979, which
also serves as the LDO input. The LDO generates a 1.8 V output
for the AD9979 core supply voltages, AVDD and DVDD. The
LDOOUT pin can then be connected directly to the AVDD and
DVDD pins. In this configuration, the LDOEN pin is tied high
to enable the LDO.
Alternatively, a separate 1.8 V regulated supply voltage may be
used to power the AVDD and DVDD pins. In this case, the
LDOOUT pin needs to be left floating, and the LDOEN pin
needs to be grounded. A typical circuit configuration for a 1.8 V
system is shown in Figure 55.
GROUNDING AND DECOUPLING
RECOMMENDATIONS
As shown in Figure 54 and Figure 55, a single ground plane is
recommended for the AD9979. This ground plane needs to be as
continuous as possible, particularly around the P-type, AI-type,
and A-type pins to ensure that all analog decoupling capacitors
provide the lowest possible impedance path between the power
and bypass pins and their respective ground pins. All high
frequency decoupling capacitors need to be located as close as
possible to the package pins.
All the supply pins must be decoupled to ground with good
quality, high frequency chip capacitors. There also needs to be
a 4.7 μF or larger bypass capacitor for each main supply, that is,
AVDD, RGVDD, HVDD, and DRVDD, although this is not
necessary for each individual pin. In most applications, it is
easier to share the supply for RGVDD and HVDD, which can
be done as long as the individual supply pins are separately
bypassed. A separate 3 V supply can be used for DRVDD, but
this supply pin still needs to be decoupled to the same ground
plane as the rest of the chip. A separate ground for DRVSS is not
recommended.
The reference bypass pins (REFT, REFB) must be decoupled to
ground as close as possible to their respective pins. The bridge
capacitor between REFT and REFB is recommended for pixel
rates greater than 40 MHz. The analog input capacitor (CCDINM,
CCDINP) also needs to be located close to the pin.
The GND connections should be tied to the lowest impedance
ground plane on the PCB. Performance does not degrade if
several of these GND connections are left unconnected for
routing purposes.
Rev. C | Page 38 of 56