ADSP-21266_07 Datasheet, PDF (37/44 Pages) Analog Devices – Embedded Processor

OUTPUT DRIVE CURRENTS
Figure 29 shows typical I-V characteristics for the output driv-
ers of the ADSP-21266. The curves represent the current drive
capability of the output drivers as a function of output voltage.
40
30
VOH
3.3V, 25°C
20
3.47V, –45°C
10
3.11V, 125°C
0
–10
–20
–30
–40
0
VOL
0.5
3.11V, 125°C
3.3V, 25°C
3.47V, –45°C
1
1.5
2
2.5
3
3.5
SWEEP (VDDEXT) VOLTAGE (V)
Figure 29. Typical Drive
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 13 on Page 19 through Table 34 on Page 36. These include
output disable time, output enable time, and capacitive loading.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 31. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
TO
OUTPUT
PIN
50⍀
1.5V
30pF
Figure 30. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
INPUT
OR
OUTPUT ^1.5V
1.5V
Figure 31. Voltage Reference Levels for AC Measurements
ADSP-21266
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 30). Figure 33 shows graphically
how output delays and holds vary with load capacitance (note
that this graph or derating does not apply to output disable
delays). The graphs of Figure 32, Figure 33, and Figure 34 may
not be linear outside the ranges shown for Typical Output Delay
vs. Load Capacitance and Typical Output Rise Time (20%–80%,
V = Min) vs. Load Capacitance.
12
10
y = 0.0467x + 1.6323
RISE
FALL
8
6
4
y = 0.045x + 1.524
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 32. Typical Output Rise Time
(20%–80%, V_DDEXT = Max)
12
RISE
10
y = 0.049x + 1.5105
FALL
8
6
y = 0.0482x + 1.4604
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 33. Typical Output Rise/Fall Time
(20%–80%, V_DDEXT = Min)
Rev. C | Page 37 of 44 | October 2007