AD9863-50EBZ Datasheet, PDF (37/40 Pages) Analog Devices – Mixed-Signal Front-End (MxFE) Baseband Transceiver for Broadband Applications

AD9863
CLKIN1
CLKIN2
1
1, 2, 4, 8, 16
2
50MHz MAX
1, 2
Rx
DIGITAL
4
BLOCK
1, 5
3
5
Tx
DIGITAL
BLOCK
Rx
PATH
OUTPUT
CLOCK
FORMATTER
Tx
PATH
6
IFACE2
IFACE3
1. ALTERNATE TIMING MODE: REG 0x15, BIT 4
2. PLL MULTIPLICATION SETTING: REG 0x15, BITS 2–0
3. PLL OUTPUT DIVIDE BY 5; REG 0x15, BIT 3
4. Rx PATH DIVIDE BY 2: REG 0x15, BIT 5
5. PLL BYPASS PATH: REG 0x15, BIT 7
6. INTERP CONTROL, Tx/Rx INV IFACE3, CLK MODE, INV IFACE2, FD/HD, 12/24
Figure 58. Clock Distribution Block Diagram
Table 21. Interface Pins (IFACE1, IFACE2, IFACE3) Configuration Definition for Flexible Interface Operation
Clock
Mode Pin 1
2
4T
4R
5T
5R
7T
7R
8T
8R
Full-Duplex
Half-Duplex, 24-Bit
Half-Duplex, 12-Bit
CLKIN1,
CLKIN2
Internally
Independent Tied
Independent
Together
Internally Tied
Together
Independent
Internally Tied
Together
IFACE1
TxSync
Tx/Rx
Tx/Rx
IFACE2
Buff_CLKIN1 RxSync Optional CLKOUT
Optional CLKOUT
IFACE3
Tx Clock
Tx
Rx
Tx
Rx
Tx
Rx
Tx
Rx
Clock Clock Clock Clock Clock Clock Clock Clock
10T 10R
Clone Mode
Independent
Tx/Rx
Optional
CLKOUT
Tx
Rx
Clock Clock
The Tx clock output frequency depends on whether the data is
in interleaved or parallel (noninterleaved) configuration. Modes
1, 2, 7, 8, and 10 use Tx interleaved data and require either 2×
or 4× interpolation to be enabled.
• DAC update rate = CLKIN2 × PLL setting.
• Noninterleaved Tx data clock frequency = CLKIN2 × PLL
setting × 1/(interpolation rate).
• Interleaved Tx data clock frequency = 2 × CLKIN2 × PLL
setting × 1/(interpolation rate).
The Rx clock does not depend on whether the data is
interleaved or parallel, but it does depends on the configuration
of the timing mode: normal or alternative.
• Normal timing mode, Rx clock frequency = CLKIN1 ×
ADC div factor (if enabled).
• Alternative timing mode, Rx clock frequency = CLKIN2 ×
PLL setting × ADC div factor (if enabled).
An optional CLKOUT from IFACE2 is available as a stable
system clock running at the CLKIN1 frequency or the TxDAC
update rate, which is equal to CLKIN2 × PLL setting. Setting
the enable IFACE2 clkout register [Register 0x01, Bit 2] enables
the IFACE2 optional clock output. In FD mode the IFACE2 pin
always acts as a clock output; the enable IFACE2 pin can be
used to invert the IFACE2 output.
Configuration
The AD9863 timing for the transmit path and for the receive
path depend on the mode setting and various programmable
options. The registers that affect the output clock timing and
data input/output timing are Clk_Mode [2:0], enable IFACE2
clkout, inv clkout (IFACE3), Tx inverse sample, interpolation
control, PLL bypass, ADC clock div, alt timing mode, PLL Div5,
PLL multiplier, and PLL to IFACE2. The Clk_Mode register is
presented previously.
Table 22 shows the other register bits that are used to configure
the output clock timing and data latching options available in
the AD9863.
Rev. A | Page 37 of 40