AD9735_15 Datasheet, PDF (37/72 Pages) Analog Devices – 10-/12-/14-Bit, 1200 MSPS DACS

AD9734/AD9735/AD9736
CSB—Chip Select
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should stay
low during the entire communication cycle.
SDIO—Serial Data I/O
Data is always written into the AD973x on this pin. However,
this pin can be used as a bidirectional data line. The configu-
ration of this pin is controlled by SDIO_DIR at Reg. 0, Bit 7.
The default is Logic 0, which configures the SDIO pin as
unidirectional.
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD973x operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
MSB/LSB TRANSFERS
The AD973x serial port can support both MSB-first or LSB-first
data formats. This functionality is controlled by LSBFIRST at
Reg. 0, Bit 6. The default is MSB first (LSBFIRST = 0).
When LSBFIRST = 0 (MSB first), the instruction and data bytes
must be written from the most significant bit to the least
significant bit. Multibyte data transfers in MSB-first format start
with an instruction byte that includes the register address of the
most significant data byte. Subsequent data bytes should follow
in order from high address to low address. In MSB-first mode,
the serial port internal byte address generator decrements for
each data byte of the multibyte communication cycle.
When LSBFIRST = 1 (LSB first), the instruction and data bytes
must be written from least significant bit to most significant bit.
Multibyte data transfers in LSB-first format start with an
instruction byte that includes the register address of the least
significant data byte followed by multiple data bytes. The serial
port internal byte address generator increments for each byte of
the multibyte communication cycle.
The AD973x serial port controller data address decrements
from the data address written toward 0x00 for multibyte I/O
operations if the MSB-first mode is active. The serial port
controller address increments from the data address written
toward 0x1F for multibyte I/O operations if the LSB-first mode
is active.
NOTES ON SERIAL PORT OPERATION
The AD973x serial port configuration is controlled by Reg. 0,
Bit 4, Bit 5, Bit 6, and Bit 7. Note that the configuration changes
immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register can occur during
the middle of the communication cycle. Care must be taken to
compensate for this new configuration for the remaining bytes
of the current communication cycle. The same considerations
apply to setting the software reset, RESET (Reg. 0, Bit 5). All
registers are set to their default values except Reg. 0 and Reg. 4,
which remain unchanged.
Use of only single-byte transfers when changing serial port
configurations or initiating a software reset is highly
recommended. In the event of unexpected programming
sequences, the AD973x SPI can become inaccessible. For
example, if user code inadvertently changes the LONG_INS bit
or the LSBFIRST bit, the following bits experience unexpected
results. The SPI can be returned to a known state by writing an
incomplete byte (1 to 7 bits) of all 0s followed by 3 bytes of
0x00. This returns to MSB-first short instructions
(Reg. 0 = 0x00), so the device can be reinitialized.
CSB
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
R/W N1 N0 A4 A3 A2 A1 A0 D7N D6N D5N
D30 D20 D10 D00
Figure 69. Serial Register Interface Timing, MSB-First Write
CSB
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
SDO
R/W N1 N0 A4 A3 A2 A1 A0 D6N D5N
D30 D20 D10 D00
D7
D6N D5N
D30 D20 D10 D00
D7
Figure 70. Serial Register Interface Timing, MSB-First Read
CSB
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20
D4N D5N D6N D7N
Figure 71. Serial Register Interface Timing, LSB-First Write
CSB
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
SDO
A0 A1 A2 A3 A4 N0 N1 R/W D1₀ D2₀
D4_N D5_N D6_N D7_N
D0
D1₀ D2₀
D4_N D5_N D6_N D7_N
D0
Figure 72. Serial Register Interface Timing, LSB-First Read
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