ADSP-21364BSWZ-1AA Datasheet, PDF (36/56 Pages) Analog Devices – SHARC Processors

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I²S, or right justified with word widths of 16-, 18-,
20-, or 24-bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 29 shows the right-justified mode. Frame sync is high for
the left channel and low for the right channel. Data is valid on
the rising edge of serial clock. The MSB is delayed the minimum
in 24-bit output mode or the maximum in 16-bit output mode
from a frame sync transition, so that when there are 64 serial
clock periods per frame sync period, the LSB of the data is right-
justified to the next frame sync transition.
Table 33. S/PDIF Transmitter Right-Justified Mode
Parameter
Timing Requirement
t_RJD
FS to MSB Delay in Right-Justified Mode
16-Bit Word Mode
18-Bit Word Mode
20-Bit Word Mode
24-Bit Word Mode
Nominal
16
14
12
8
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
LSB
LEFT/RIGHT CHANNEL
t_RJD
MSB MSB–1 MSB–2
Figure 29. Right-Justified Mode
LSB+2 LSB+1 LSB
Unit
SCLK
SCLK
SCLK
SCLK
Rev. G | Page 36 of 56 | March 2011