AD9866_15 Datasheet, PDF (36/48 Pages) Analog Devices – Broadband Modem Mixed-Signal Front End

AD9866
AGC TIMING CONSIDERATIONS
When implementing a digital AGC timing loop, it is important
to consider the Rx path latency and settling time of the Rx path
in response to a change in gain setting. Figure 21 and Figure 24
show the RxPGA’s settling response to a 60 dB and 5 dB change
in gain setting when using the Tx[5:0] or PGA[5:0] port. While
the RxPGA settling time may also show a slight dependency on
the LPF’s cutoff frequency, the ADC’s pipeline delay along with
the ADIO bus interface presents a more significant delay. The
amount of delay or latency depends on whether a half- or full-
duplex is selected. An impulse response at the RxPGA’s input
can be observed after 10.0 ADC clock cycles (1/fADC) in the case
of a half-duplex interface and 10.5 ADC clock cycles in the case
of a full-duplex interface. This latency along with the RxPGA
settling time should be considered to ensure stability of the
AGC loop.
Rev. B | Page 36 of 48