AD9739A Datasheet, PDF (36/44 Pages) Analog Devices – 14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter

AD9739A
CLOCK INPUT CONSIDERATIONS
V_REF
V_T
V_CC
50Ω 50Ω
50Ω
10nF _D
D
50Ω 10nF
V_EE
ADCLK914
Q
Q
50Ω 50Ω
10nF
100Ω
10nF
Figure 89. ADCLK914 Interface to the AD9739A CLK Input
AD9739A
DACCLK_P
DACCLK_N
FREF
ADF4350
PLL
VCO
V_VCO
DIV-BY-2^N
N=0–4
RF_OUTA+
RF_OUTA–
RF_OUTA+
RF_OUTA–
3.9nH
1nF
100Ω
1nF
1.8V p-p
AD9739A
DACCLK_P
DACCLK_N
Figure 90. ADF4350 Interface to the AD9739A CLK Input
The quality of the clock source and its drive strength are
important considerations in maintaining the specified ac
performance. The phase noise and spur characteristics of the
clock source should be selected to meet the target application
requirements. Phase noise and spurs at a given frequency offset
on the clock source are directly translated to the output signal.
It can be shown that the phase noise characteristics of a
reconstructed output sine wave are related to the clock source
by 20 × log10(fOUT/fCLK) when the DAC clock path contribution,
along with thermal and quantization effects, are negligible.
The AD9739A clock receiver provides optimum jitter
performance when driven by a fast slew rate originating from
the LVPECL or CML output drivers. For a low jitter sinusoidal
clock source, the ADCLK914 can be used to square-up the
signal and provide a CML input signal for the AD9739A clock
receiver. Note that all specifications and characterization
presented in the data sheet are with the ADCLK914 driven by a
high quality RF signal generator with the clock receiver biased
at a 800 mV level.
Figure 90 shows a clock source based on the ADF4350 low
phase noise/jitter PLL. The ADF4350 can provide output
frequencies from 140 MHz up to 4.4 GHz with jitter as low as
0.5 ps rms. Each single-ended output can provide a squared-up
output level that can be varied from −4 dBm to +5 dBm
allowing for >2 V p-p output differential swings. The ADF4350
also includes an additional CML buffer that can be used to drive
another AD9739A device.
4-BIT PMOS
IOUT ARRAY
VDDC
DACCLK_P
DACCLK_N
CLKx_OFFSET
DIR_x = 0
ESD
CLKx_OFFSET
DIR_x = 0
4-BIT NMOS
IOUT ARRAY
VSSC
Figure 91. Clock Input and Common-Mode Control
The AD9739A clock receiver features the ability to indepen-
dently adjust the common-mode level of its inputs over a span
of ±100 mV centered about is mid-supply point (that is,
VDDC/2) as well as an offset for hysteresis purposes. Figure 91
shows the equivalent input circuit of one of the inputs. ESD
diodes are not shown for clarity purposes. It has been found
through characterization that the optimum setting is for both
inputs to be biased at approximately 0.8 V. This can be achieved
by writing a 0x0F (corresponding to a −15) setting to both cross
controller registers (that is, Register 0x22 and Register 0x23).
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