AD9265_13 Datasheet, PDF(36/45 Page) Analog Devices – 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter

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AD9265_13 Datasheet, PDF (36/45 Pages) Analog Devices – 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter

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Data Sheet

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,

the SDIO/DCS pin and the SCLK/DFS pin serve as standalone

CMOS-compatible control pins. When the device is powered

up, it is assumed that the user intends to use the pins as static

control lines for the duty cycle stabilizer and output data format

feature control. In this mode, connect the CSB chip select to

AVDD, which disables the serial port interface.

The OEB pin, the DITHER pin, the LVDS pin, the LVDS_RS

pin, and the PDWN pin are active control lines in both external

pin mode and SPI mode. The input from these pins or the SPI

the part.

Table 15. Mode Selection

External

Voltage

SDIO/DCS SVDD (default)

AGND

SCLK/DFS SVDD

AGND (default)

OEB

DRVDD

AGND (default)

PDWN

AVDD

LVDS

LVDS_RS

AGND (default)

AVDD

AGND (default)

AVDD

DITHER

AGND (default)

AVDD

Configuration

Duty cycle stabilizer enabled

Duty cycle stabilizer disabled

Twos complement enabled

Offset binary enabled

Outputs in high impedance

Outputs enabled

Chip in power-down or standby

mode

Normal operation

CMOS output mode

LVDS output mode

ANSI LVDS output levels

Reduced swing LVDS output

levels

Dither disabled

Dither enabled

AD9265

SPI ACCESSIBLE FEATURES

Table 16 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in Application Note AN-877, Interfacing to High Speed ADCs via

SPI. The AD9265 part-specific features are described in detail

following Table 17, the external memory map register table.

Table 16. Features Accessible Using the SPI

Feature

Name

Description

Mode

Allows the user to set either power-down mode or

standby mode

Clock

Allows the user to access the DCS, set the clock

divider, set the clock divider phase, and enable

the SYNC input

Offset

Allows the user to digitally adjust the converter

offset

Test I/O

Allows the user to set test modes to have known

data on output bits

Output Mode Allows the user to set the output mode

Output Phase Allows the user to set the output clock polarity

Output Delay Allows the user to vary the DCO delay

VREF

Allows the user to set the reference voltage

CSB

tDS

tDH

tHIGH

tLOW

tCLK

SCLK DONâT CARE

SDIO DONâT CARE

R/W

A12

A11

A10

DONâT CARE

Figure 84. Serial Port Interface Timing Diagram

Rev. C | Page 35 of 44

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