ADUC814 Datasheet, PDF (35/72 Pages) Analog Devices – MicroConverter, Small Package 12-Bit ADC with Embedded Flash MCU

ADuC814
DACxH/L
Function
SFR Address
Power-On Default
Bit Addressable
DAC0 and DAC1 Data Registers
DAC Data Registers, written by the user to update the DAC outputs.
DAC0L (DAC0 data low byte) –> F9H DAC0H (DAC0 data high byte) –> FAH;
DAC1L (DAC1 data low byte) –> FBH DAC1H (DAC1 data high byte) –> FCH
00H –> Both DAC0 and DAC1 data registers.
No –> Both DAC0 and DAC1 data registers.
The 12-bit DAC data should be written into DACxH/L right-justified such that DACL contains the lower eight bits, and the lower nibble
of DACH contains the upper four bits.
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is illustrated in Figure 38. Features of this architecture
include inherent guaranteed monotonicity and excellent differ-
ential linearity.
AV_DD
ADuC814
V_REF
R
R
R
R
OUTPUT
BUFFER
DAC0
HIGH Z
DISABLE
(FROM MCU)
R
Figure 38. Resistor String DAC Functional Equivalent
As illustrated in Figure 38, the reference source for each DAC is
user selectable in software. It can be either AVDD or VREF. In
0 V-to-AVDD mode, the DAC output transfer function spans
from 0 V to the voltage at the AVDD pin. In 0 V-to-VREF mode,
the DAC output transfer function spans from 0 V to the internal
VREF, or if an external reference is applied, the voltage at the VREF
pin. The DAC output buffer features a true rail-to-rail output
stage implementation. This means that, unloaded, each output is
capable of swinging to within less than 100 mV of both AVDD
and ground. Moreover, the DAC’s linearity specification (when
driving a 10 kΩ resistive load to ground) is guaranteed through
the full transfer function except Codes 0 to 48, and, in 0 V-to-
AVDD mode only, Codes 3945 to 4095. Linearity degradation
near ground and VDD is caused by saturation of the output
buffer, and a general representation of its effects (neglecting
offset and gain error) is illustrated in Figure 39. The dotted line
in Figure 39 indicates the ideal transfer function, and the solid
line represents what the transfer function might look like with
endpoint nonlinearities due to saturation of the output buffer.
Note that Figure 39 represents a transfer function in 0 V-to-VDD
mode only. In 0 V-to-VREF mode (with VREF < VDD), the lower
nonlinearity would be similar, but the upper portion of the
transfer function would follow the ideal line right to the end
(VREF in this case, not VDD), showing no signs of upper endpoint
linearity error.
V_DD
V_DD–50mV
V_DD–100mV
100mV
50mV
0mV
000H
FFFH
Figure 39. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in Figure 39
get worse as a function of output loading. Most ADuC814
specifications assume a 10 kΩ resistive load to ground at the
DAC output. As the output is forced to source or sink more
current, the nonlinear regions at the top or bottom (respectively)
of Figure 39 become larger. With larger current demands, this
can significantly limit output voltage swing. Figure 40 and
Figure 41 illustrate this behavior. Note that the upper trace in
each of these figures is valid only for an output range selection
of 0 V-to-AVDD. In 0 V-to-VREF mode, DAC loading does not
cause high-side voltage drops as long as the reference voltage
remains below the upper trace in the corresponding figure. For
example, if AVDD = 3 V and VREF = 2.5 V, the high-side voltage is
not affected by loads less than 5 mA. But around 7 mA, the
upper curve in Figure 41 drops below 2.5 V (VREF), indicating
that at these higher currents the output cannot reach VREF.
Rev. A | Page 35 of 72