ADSP-BF538F_15 Datasheet, PDF (35/60 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF538/ADSP-BF538F
Table 29. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter
Timing Requirement
t_WBR
BR Pulse Width
Switching Characteristics
t_SD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
t_SE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
t_DBG
CLKOUT High to BG High Setup
t_EBG
CLKOUT High to BG Deasserted Hold Time
t_DBH
CLKOUT High to BGH High Setup
t_EBH
CLKOUT High to BGH Deasserted Hold Time
Min
2 × t_SCLK
Max
4.5
4.5
3.6
3.6
3.6
3.6
Unit
ns
ns
ns
ns
ns
ns
ns
CLKOUT
BR
AMSx
ADDR 19-1
ABE1-0
AWE
ARE
BG
BGH
t_WBR
tSD
tSD
tSD
t_DBG
tDBH
tSE
tSE
tSE
t_EBG
tEBH
Figure 18. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Rev. E | Page 35 of 60 | November 2013