ADSP-21367 Datasheet, PDF (35/48 Pages) Analog Devices – SHARC Processor

Preliminary Technical Data
SPDIF Receiver
The following sections describe timing as it relates to the SPDIF
receiver.
Internal Digital PLL Mode
In internal Digital Phase-locked Loop mode the internal PLL
(Digital PLL) generates the 512 × Fs clock.
Table 29. SPDIF Receiver Internal Digital PLL Mode Timing
Parameter
Switching Characteristics
t_DFSI
t_HOFSI
LRCLK Delay After SCLK
LRCLK Hold After SCLK
t_DDTI
t_HDTI
t_SCLKIW¹
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit SCLK Width
t_CCLK
Core Clock Period
1 _{SCLK frequency is 64 x FS where FS = the frequency of LRCLK.}
Min
Max
5
–2
5
–2
40
5
ADSP-21367
Unit
ns
ns
ns
ns
ns
ns
DRIVE EDGE
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(DATA CHANNEL A/B)
t_HOFSI
t_HDTI
t_DFSI
t_SCLKIW
t_SFSI
t_DDTI
SAMPLE EDGE
t_HFSI
Figure 26. SPDIF Receiver Internal Digital PLL Mode Timing
Rev. PrA | Page 35 of 48 | November 2004