ADSP-21261 Datasheet, PDF (35/44 Pages) Analog Devices – SHARC Embedded Processor

Table 30. SPI Protocol—Slave
Parameter
Timing Requirements
t_SPICLKS
t_SPICHS
t_SPICLS
t_SDSCO
t_HDS
t_SSPIDS
t_HSPIDS
t_SDPPW
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE = 0)
Switching Characteristics
t_DSOE
t_DSDHI
t_DDSPIDS
t_HDSPIDS
t_DSOV
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
ADSP-21261
Min
4 × t_CCLK
2 × t_CCLK – 2
2 × t_CCLK – 2
2 × t_CCLK + 1
2 × t_CCLK + 1
2 × t_CCLK
2
2
2 × t_CCLK
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
2 × t_CCLK – 2
5
ns
5
ns
7.5
ns
ns
5 × t_CCLK + 2 ns
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
t_SDSCO
SPICLK
(CP = 1)
(INPUT)
t_DSOE
t_{S P IC H S}
t_SPICLS
t_DDSPIDS
t_SPICLS
t_SPICHS
t_SPICLKS
t_HDS
t_DDSPIDS
MISO
(OUTPUT)
MSB
CPHASE = 1
t_SSPIDS
MOSI
(INPUT)
t_DSOV
t_{D S O E}
MISO
(OUTPUT)
MSB VALID
MSB
t_DDSPIDS
CPHASE = 0
MOSI
(INPUT)
MSB VALID
t_SSPIDS
LSB
t_HSPIDS
LSB VALID
t_HDSPIDS
LSB
t_SSPIDS
t_HSPIDS
LSB VALID
t_SDPPW
t_DSDHI
t_HDSPIDS
t_DSDHI
Figure 26. SPI Protocol—Slave
Rev. 0 | Page 35 of 44 | March 2006