ADF7021BCPZ-RL Datasheet, PDF (35/64 Pages) Analog Devices – High Performance Narrow-Band Transceiver IC

Data Sheet
ADF7021
3FSK Viterbi Detector Setup
The Viterbi detector can be used for 3FSK data detection. This
is activated by setting R13_DB11 to Logic 1.
The Viterbi path memory length is programmable in steps of 4,
6, 8, or 32 bits (VITERBI_PATH_MEMORY, R13_DB[13:14]).
The path memory length should be set equal to or greater than
the maximum number of consecutive 0s in the interleaved
transmit bit stream.
The Viterbi detector also uses threshold levels to implement the
maximum likelihood detection algorithm. These thresholds are
programmable via the 3FSK/4FSK_SLICER_THRESHOLD bits
(R13_DB[4:10]).
These bits are assigned as follows:
3FSK/4FSK_SLICER_THRESHOLD =
57 ×
Transmit
Frequency Deviation × K
100 ×10³

where K is the value calculated for correlator discriminator
bandwidth.
3FSK Threshold Detector Setup
To activate threshold detection of 3FSK, R13_DB11 should be
set to Logic 0. The 3FSK/4FSK_SLICER_THRESHOLD bits
(R13_DB[4:10]) should be set as outlined in the 3FSK Viterbi
Detector Setup section.
3FSK CDR Setup
In 3FSK, a transmit preamble of at least 40 bits of continuous 1s
is recommended to ensure a maximum number of symbol
transitions for the CDR to acquire lock.
The clock and data recovery for 3FSK requires a number of
parameters in Register 13 to be set (see Table 20).
4FSK Threshold Detector Setup
The threshold for the 4FSK detector is set using the
3FSK/4FSK_SLICER_THRESHOLD bits (R13_DB[4:10]).
The threshold should be set according to
3FSK/4FSK_SLICER_THRESHOLD =
78× _{}
4FSK
Outer Tx Deviation
100 ×10³
×
K

where K is the value calculated for correlator discriminator
bandwidth.
Table 20. 3FSK CDR Settings
Parameter
PHASE_CORRECTION (R13_DB12)
3FSK_CDR_THRESHOLD (R13_DB[15:21])
3FSK_PREAMBLE_TIME_VALIDATE (R13_DB [22:25])
Recommended Setting
1
62
× _{}
Transmit
Frequency Deviation×
100 ×10³
K

where K is the value calculated for
correlator discriminator bandwidth.
1111
Purpose
Phase correction on
Sets CDR decision threshold levels
Preamble detector time qualifier
Rev. B | Page 35 of 64