ADV7173_15 Datasheet, PDF (34/60 Pages) Analog Devices – Digital PAL/NTSC Video Encoder with Six DACs

ADV7172/ADV7173
TIMING REGISTER 0 (TR07–TR00)
(Address (SR4–SR0) = 0AH)
Figure 52 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7172/ADV7173 is in master
or slave mode.
Timing Mode Selection (TR02–TR01)
These bits control the timing mode of the ADV7172/ADV7173.
These modes are described in more detail in the Timing and
Control section of the data sheet.
BLANK Input Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode or whether BLANK is internally generated.
Luma Delay (TR05–TR04)
These bits control the addition of a delay to the luminance with
respect to the chrominance. Each bit represents a delay of 74 ns.
Min Luma Value (TR06)
The bit is used to control the minimum luma value output by
the ADV7172/ADV7173. When this bit is set to (“1”), the luma
is limited to 7.5 IRE below the blank level. When this bit is set
to (“0”), the luma value can be as low as the sync bottom level.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changed to a new timing mode.
TR07
TR06
TIMING
REGISTER RESET
TR07
MIN LUMA VALUE
TR06
0 LUMA MIN =
SYNC BOTTOM
1 LUMA MIN =
BLANK –7.5 IRE
TR05
TR04
TR03
TR02
TR01
TR00
BLANK INPUT
CONTROL
TR03
0 ENABLE
1 DISABLE
MASTER/SLAVE
CONTROL
TR00
0 SLAVE TIMING
1 MASTER TIMING
LUMA DELAY
TR05 TR04
0 0 0ns DELAY
0 1 74ns DELAY
1 0 148ns DELAY
1 1 222ns DELAY
TIMING MODE
SELECTION
TR02 TR01
0 0 MODE 0
0 1 MODE 1
1 0 MODE 2
1 1 MODE 3
Figure 52. Timing Register 0
–34–
REV. B