ADSP-21990_15 Datasheet, PDF (34/50 Pages) Analog Devices – Mixed-Signal DSP Controller

ADSP-21990
5 _{Only applies to SPORT.}
6 _{MCE = 1, TFS enable, and TFS valid follow tDDTENFS and tDDTLFSE.}
7 _{If external RFSD/TFS setup to RCLK/TCLK > 0.5tLSCK, tDDTLSCK and tDTENLSCK apply; otherwise, tDDTLFSE and tDTENLFS apply.}
DATA RECEIVE-INTERNAL CLOCK
DRIVE
EDGE
t_SCLKIW
RCLK
t_DFSE
t_HOFSE
t_SFSI
RFS
SAMPLE
EDGE
t_HFSI
t_SDRI
t_HDRI
DR
DATA RECEIVE-EXTERNAL CLOCK
DRIVE
EDGE
t_SCLKW
RCLK
t_DFSE
t_HOFSE
t_SFSE
RFS
SAMPLE
EDGE
t_HFSE
t_SDRE
t_HDRE
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT-INTERNAL CLOCK
DRIVE
EDGE
t_SCLKIW
TCLK
t_DFSE
t_HOFSE
t_SFSI
SAMPLE
EDGE
t_HFSI
TFS
t_HDTI ^tDDTI
DATA TRANSMIT-EXTERNAL CLOCK
DRIVE
EDGE
t_SCLKW
TCLK
t_DFSE
t_HOFSE
t_SFSE
TFS
t_DDTE
t_HDTE
SAMPLE
EDGE
t_HFSE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
TCLK (EXT)
TFS (“LATE,” EXT)
DT
TCLK (INT)
TFS (“LATE,” INT)
DRIVE
EDGE
t_DDTEN
DRIVE
EDGE
t_DDTIN
DT
TCLK/RCLK
TCLK/RCLK
DRIVE
EDGE
t_DDTTE
DRIVE
EDGE
t_DDTTI
Figure 13. Serial Port
Rev. A | Page 34 of 50 | August 2007