AD9887AKSZ-170 Datasheet, PDF (34/52 Pages) Analog Devices – Dual Interface for Flat Panel Display

AD9887A
Address
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
Read and
Write, or
Read Only
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
Default
Bits Value
*****0**
******0*
*******1
7:0 00100000
7:0 ***1****
****0***
*****0**
******0*
*******0
7:5 0*******
*0******
**0*****
7:2 10111***
*****1**
7:0 00000000
7:0 00000000
7:0 00000000
7:0 11111111
7:0 00000000
7:0 00000***
*****1**
******1*
*******1
7:0 *_*****
7:0 11111111
7:0 10000100
7:0 0*******
*0******
**0*****
***0****
****1***
*****0**
7:0 00000000
Register Name
Sync Separator
Threshold
Control Bits
Polarity Status
Control Bits
Precoast
Postcoast
Test Register
Test
4:2:2 Control
TDMS Gain Control
Description
Bit 2—Output Vsync Select. Logic 0 selects raw Vsync as the output
Vsync. Logic 1 selects sync separator output as the active Vsync. Note
that the indicated Vsync is used only if Bit 3 is set to Logic 1.
Bit 1—COAST Select. Logic 0 selects the COAST input pin used for the
PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
Bit 0—PWRDN. Full Chip Power-Down, active low. Logic 0 = full chip
power-down; Logic 1 = normal.
Sync Separator Threshold. Sets the number of clock cycles that the sync
separator counts before toggling high or low. This should be set to a
number greater than the maximum Hsync or equalization pulse width.
Bit 4—Must be set to 1 for proper operation.
Bit 3—Must be set to 0 for proper operation.
Bit 2—Scan Enable. Logic 0 = scan function disabled; Logic 1 = scan
function enabled.
Bit 1—COAST Input Polarity Override. Logic 0 = polarity determined by
chip; Logic 1 = polarity determined by user via Bit 6 in Register 0x0F.
Bit 0—HSYNC Input Polarity Override. Logic 0 = polarity determined
by chip; Logic 1 = polarity determined by user via Bit 7 in Register 0x0F.
Bit 7—Hsync Input Polarity Status. Logic 0 = active low; Logic 1 =
active high.
Bit 6—Vsync Output Polarity Status. Logic 0 = active high; Logic 1 =
active low.
Bit 5—Coast Input Polarity Status. Logic 0 = active low; Logic 1 =
active high.
Bits[7:3]—Sync-on-Green Slicer Threshold.
Bit 2—Must be set to 0 for proper operation.
Sets the number of Hsyncs prior to Vsync before which coast goes
active.
Sets the number of Hsyncs following Vsync before coast goes active.
Must be set to default for proper operation.
Must be set to 01000001 for proper operation.
Set to 0x00 for autogain mode and 0x10 for manual-gain mode
Bits [7:3]—Set to 00000*** for autogain mode and 00101*** for
manual-gain mode
Bit 2—CbCr Output Order.
Bit 1—Must be set to 0 for standard input sampling.
Bit 0—Output Format Mode Select. Logic 1 = 4:4:4 mode; Logic 0 =
4:2:2 mode.
HDCP Keys Detected. Logic 0 = not detected; Logic 1 = detected.
Must set to 0xFF for proper operation.
Must set to 0x84 for proper operation.
Bit 7—HDCP A0 Serial Address Bit. For Logic 0, Address = 0x74. For
Logic 1, Address = 0x76.
Bit 6—MDA Pin Select. For Logic 0, Pin 49 = Ctrl3 signal. For Logic 1,
Pin 49 = MDA for HDCP.
Bit 5—Analog Input Bandwidth Control. Logic 0 = high.
Bit 4—MDA/MCL Three-State. Logic 0 = three-state; Logic 1 = normal
operation.
Bit 3—External Oscillator. Logic 1 = internal; Logic 0 = use external
oscillator on A0.
Normal Operation.
Set to 0x00 for autogain mode and 0x64 for manual-gain mode.
Rev. B | Page 34 of 52